Lines Matching full:control
32 * Control Register
42 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
53 * Multiplex Control
56 * multiplex control 2
58 u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
60 u32 devdisr; /* 0x.0070 - Device Disable Control */
63 u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
65 u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
69 * Control Register
82 * Control Register
84 u32 ectrstcr; /* 0x.0098 - Exception reset control register */
89 u32 rstcr; /* 0x.00b0 - Reset Control Register */
94 u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
97 u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
98 u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
104 u32 ircr; /* 0x.0900 - Infrared Control Register */
106 u32 dmacr; /* 0x.0908 - DMA Control Register */
108 u32 elbccr; /* 0x.0914 - eLBC Control Register */
116 u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
118 u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
123 u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
124 u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
126 u32 itcr; /* 0x.0f2c - Internal transaction control
130 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
131 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
134 /* Alternate function signal multiplex control */
181 * Set the DMA external control bits in the GUTS
183 * The DMA external control bits in the PMUXCR are only meaningful for
220 __be32 cdozcr; /* 0x000c Core Doze Control Register */
224 __be32 cnapcr; /* 0x001c Core Nap Control Register */
233 __be32 powmgtcsr; /* 0x0040 PM Control&Status Register */
236 __be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */
250 __be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */
259 __be32 tph10setr0; /* Thread PH10 Set Control Register */
261 __be32 tph10clrr0; /* Thread PH10 Clear Control Register */
268 __be32 pcph15setr; /* Physical Core PH15 Set Control Register */
269 __be32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
273 __be32 pcph20setr; /* Physical Core PH20 Set Control Register */
274 __be32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
279 __be32 pcph30setr; /* Physical Core PH30 Set Control Register */
280 __be32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
283 __be32 ippwrgatecr; /* IP Power Gating Control Register */
285 __be32 powmgtcsr; /* Power Management Control & Status Reg */
290 __be32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
300 __be32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
305 __be32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
307 __be32 clpcl10setr; /* Cluster PCL30 Set Control Register */
308 __be32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */