Lines Matching defs:ccsr_rcpm_v1
216 struct ccsr_rcpm_v1 { struct
217 u8 res0000[4];
218 __be32 cdozsr; /* 0x0004 Core Doze Status Register */
219 u8 res0008[4];
220 __be32 cdozcr; /* 0x000c Core Doze Control Register */
221 u8 res0010[4];
222 __be32 cnapsr; /* 0x0014 Core Nap Status Register */
223 u8 res0018[4];
224 __be32 cnapcr; /* 0x001c Core Nap Control Register */
225 u8 res0020[4];
226 __be32 cdozpsr; /* 0x0024 Core Doze Previous Status Register */
227 u8 res0028[4];
228 __be32 cnappsr; /* 0x002c Core Nap Previous Status Register */
229 u8 res0030[4];
230 __be32 cwaitsr; /* 0x0034 Core Wait Status Register */
231 u8 res0038[4];
232 __be32 cwdtdsr; /* 0x003c Core Watchdog Detect Status Register */
233 __be32 powmgtcsr; /* 0x0040 PM Control&Status Register */
235 u8 res0044[12];
236 __be32 ippdexpcr; /* 0x0050 IP Powerdown Exception Control Register */
237 u8 res0054[16];
238 __be32 cpmimr; /* 0x0064 Core PM IRQ Mask Register */
239 u8 res0068[4];
240 __be32 cpmcimr; /* 0x006c Core PM Critical IRQ Mask Register */
241 u8 res0070[4];
242 __be32 cpmmcmr; /* 0x0074 Core PM Machine Check Mask Register */
243 u8 res0078[4];
244 __be32 cpmnmimr; /* 0x007c Core PM NMI Mask Register */
245 u8 res0080[4];
246 __be32 ctbenr; /* 0x0084 Core Time Base Enable Register */
247 u8 res0088[4];
248 __be32 ctbckselr; /* 0x008c Core Time Base Clock Select Register */
249 u8 res0090[4];
250 __be32 ctbhltcr; /* 0x0094 Core Time Base Halt Control Register */
251 u8 res0098[4];
252 __be32 cmcpmaskcr; /* 0x00a4 Core Machine Check Mask Register */