Lines Matching +full:idle +full:- +full:mode +full:- +full:mask

18 #include <linux/clk-provider.h>
22  * struct clk_omap_reg - OMAP register declaration
34  * struct dpll_data - DPLL registers and integration data
36  * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
37  * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
40  * @control_reg: register containing the DPLL mode bitfield
41  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
48  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
50  * @min_divider: minimum valid non-bypass divider value (actual)
51  * @max_divider: maximum valid non-bypass divider value (actual)
54  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
55  * @idlest_reg: register containing the DPLL idle status bitfield
56  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
57  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
58  * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
60  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
61  * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
62  * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
69  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
76  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
77  * @last_rounded_n) should be separated from the runtime-fixed fields
78  * and placed into a different structure, so that the runtime-fixed data
79  * can be placed into read-only space.
119  * struct clk_hw_omap_ops - OMAP clk ops
122  *		    basically converts CM_ICLKEN* <-> CM_FCLKEN*
138  * struct clk_hw_omap - OMAP struct clk
175  *     clock is put to no-idle mode.
182  *     should be used.  This is a temporary solution - a better approach
183  *     would be to associate clock type-specific data with the clock,
186 #define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
193 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
214  * struct ti_clk_ll_ops - low-level ops for clocks
217  * @clk_rmw: pointer to register read-modify-write function
224  * Low-level ops are generally used by the basic clock types (clk-gate,
225  * clk-mux, clk-divider etc.) to provide support for various low-level
227  * by board code. Low-level ops also contain some other platform specific
233 	void	(*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg);
316 static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }  in omap3430_clk_legacy_init()
317 static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }  in omap3430es1_clk_legacy_init()
318 static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }  in omap36xx_clk_legacy_init()
319 static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }  in am35xx_clk_legacy_init()