Lines Matching +full:device +full:- +full:specific
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42 * struct clk_rate_request - Structure encoding the clk constraints that
64 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
75 * struct clk_ops - Callback operations for hardware clocks; these are to
122 * Returns the calculated rate. Optional, but recommended - if
138 * Returns 0 on success, -EERROR otherwise.
154 * Returns 0 on success, -EERROR otherwise.
165 * Returns 0 on success, -EERROR otherwise.
170 * Returns the calculated accuracy. Optional - if this op is not
175 * Returned values are 0-359 degrees on success, negative
180 * 0-359. Return 0 on success, otherwise -EERROR.
189 * and >= numerator) Return 0 on success, otherwise -EERROR.
191 * @init: Perform platform-specific initialization magic.
198 * Returns 0 on success, -EERROR otherwise.
202 * @debug_init: Set up type-specific debugfs entries for this clock. This
206 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
216 * (eg. when a device is opened), and clk_enable when the clock is actually
258 * struct clk_parent_data - clk parent information
272 * struct clk_init_data - holds init data that's common to all clocks and is
283 * @flags: framework-level hints and quirks
297 * struct clk_hw - handle for traversing from a struct clk to its corresponding
298 * hardware-specific structure. struct clk_hw should be declared within struct
305 * @clk: pointer to the per-user struct clk instance that can be used to call
328 * struct clk_fixed_rate - fixed-rate clock
329 * @hw: handle between common and hardware-specific interfaces
332 * @flags: hardware specific flags
335 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
348 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
354 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
358 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
360 * @dev: device that is registering this clock
363 * @flags: framework-specific flags
364 * @fixed_rate: non-adjustable clock rate
370 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
372 * @dev: device that is registering this clock
375 * @flags: framework-specific flags
376 * @fixed_rate: non-adjustable clock rate
383 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
385 * @dev: device that is registering this clock
388 * @flags: framework-specific flags
389 * @fixed_rate: non-adjustable clock rate
397 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
399 * @dev: device that is registering this clock
402 * @flags: framework-specific flags
403 * @fixed_rate: non-adjustable clock rate
404 * @fixed_accuracy: non-adjustable clock accuracy
413 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
415 * @dev: device that is registering this clock
418 * @flags: framework-specific flags
419 * @fixed_rate: non-adjustable clock rate
420 * @fixed_accuracy: non-adjustable clock accuracy
428 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
430 * @dev: device that is registering this clock
433 * @flags: framework-specific flags
434 * @fixed_rate: non-adjustable clock rate
435 * @fixed_accuracy: non-adjustable clock accuracy
449 * struct clk_gate - gating clock
451 * @hw: handle between common and hardware-specific interfaces
454 * @flags: hardware-specific flags
460 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
463 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
464 * of this register, and mask of gate bits are in higher 16-bit of this
465 * register. While setting the gate bits, higher 16-bit should also be
467 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
486 struct clk_hw *__clk_hw_register_gate(struct device *dev,
493 struct clk *clk_register_gate(struct device *dev, const char *name,
498 * clk_hw_register_gate - register a gate clock with the clock framework
499 * @dev: device that is registering this clock
502 * @flags: framework-specific flags for this clock
505 * @clk_gate_flags: gate-specific flags for this clock
514 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
516 * @dev: device that is registering this clock
519 * @flags: framework-specific flags for this clock
522 * @clk_gate_flags: gate-specific flags for this clock
531 * clk_hw_register_gate_parent_data - register a gate clock with the clock
533 * @dev: device that is registering this clock
536 * @flags: framework-specific flags for this clock
539 * @clk_gate_flags: gate-specific flags for this clock
557 * struct clk_divider - adjustable divider clock
559 * @hw: handle between common and hardware-specific interfaces
570 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
574 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
576 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
581 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
582 * of this register, and mask of divider bits are in higher 16-bit of this
583 * register. While setting the divider bits, higher 16-bit should also be
585 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
587 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
589 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
592 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
606 #define clk_div_mask(width) ((1 << (width)) - 1)
636 struct clk_hw *__clk_hw_register_divider(struct device *dev,
642 struct clk *clk_register_divider_table(struct device *dev, const char *name,
648 * clk_register_divider - register a divider clock with the clock framework
649 * @dev: device registering this clock
652 * @flags: framework-specific flags
656 * @clk_divider_flags: divider-specific flags for this clock
665 * clk_hw_register_divider - register a divider clock with the clock framework
666 * @dev: device registering this clock
669 * @flags: framework-specific flags
673 * @clk_divider_flags: divider-specific flags for this clock
682 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
684 * @dev: device registering this clock
687 * @flags: framework-specific flags
691 * @clk_divider_flags: divider-specific flags for this clock
701 * clk_hw_register_divider_parent_data - register a divider clock with the clock
703 * @dev: device registering this clock
706 * @flags: framework-specific flags
710 * @clk_divider_flags: divider-specific flags for this clock
720 * clk_hw_register_divider_table - register a table based divider clock with
722 * @dev: device registering this clock
725 * @flags: framework-specific flags
729 * @clk_divider_flags: divider-specific flags for this clock
740 * clk_hw_register_divider_table_parent_hw - register a table based divider
742 * @dev: device registering this clock
745 * @flags: framework-specific flags
749 * @clk_divider_flags: divider-specific flags for this clock
761 * clk_hw_register_divider_table_parent_data - register a table based divider
763 * @dev: device registering this clock
766 * @flags: framework-specific flags
770 * @clk_divider_flags: divider-specific flags for this clock
787 * struct clk_mux - multiplexer clock
789 * @hw: handle between common and hardware-specific interfaces
794 * @flags: hardware-specific flags
801 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
802 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
803 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
804 * register, and mask of mux bits are in higher 16-bit of this register.
805 * While setting the mux bits, higher 16-bit should also be updated to
807 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
809 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
811 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
837 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
844 struct clk *clk_register_mux_table(struct device *dev, const char *name,
852 (flags), (reg), (shift), BIT((width)) - 1, \
865 (shift), BIT((width)) - 1, (clk_mux_flags), \
871 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
877 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
889 * struct clk_fixed_factor - fixed multiplier and divider clock
891 * @hw: handle between common and hardware-specific interfaces
909 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
913 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
919 * struct clk_fractional_divider - adjustable fractional divider clock
921 * @hw: handle between common and hardware-specific interfaces
932 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
936 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
962 struct clk *clk_register_fractional_divider(struct device *dev,
966 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
973 * struct clk_multiplier - adjustable multiplier clock
975 * @hw: handle between common and hardware-specific interfaces
985 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
990 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
992 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1014 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1016 * @hw: handle between common and hardware-specific interfaces
1017 * @mux_hw: handle between composite and hardware-specific mux clock
1018 * @rate_hw: handle between composite and hardware-specific rate clock
1019 * @gate_hw: handle between composite and hardware-specific gate clock
1039 struct clk *clk_register_composite(struct device *dev, const char *name,
1045 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1052 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1058 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1067 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1068 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1070 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1071 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1075 void devm_clk_unregister(struct device *dev, struct clk *clk);
1078 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1122 dst->clk = src->clk; in __clk_hw_set_clk()
1123 dst->core = src->core; in __clk_hw_set_clk()
1165 * routines, one at of_clk_init(), and one at platform device probe
1311 int devm_of_clk_add_hw_provider(struct device *dev,
1316 void devm_of_clk_del_provider(struct device *dev);
1345 static inline int devm_of_clk_add_hw_provider(struct device *dev, in devm_of_clk_add_hw_provider()
1353 static inline void devm_of_clk_del_provider(struct device *dev) {} in devm_of_clk_del_provider()
1357 return ERR_PTR(-ENOENT); in of_clk_src_simple_get()
1362 return ERR_PTR(-ENOENT); in of_clk_hw_simple_get()
1367 return ERR_PTR(-ENOENT); in of_clk_src_onecell_get()
1372 return ERR_PTR(-ENOENT); in of_clk_hw_onecell_get()