1 /* SPDX-License-Identifier: GPL-2.0 */
3  *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4  *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14  * top-level framework.  custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
29 #define CLK_SET_RATE_UNGATE	BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
42  * struct clk_rate_request - Structure encoding the clk constraints that
43  * a clock user might require.
45  * @rate:		Requested clock rate. This field will be adjusted by
46  *			clock drivers according to hardware capabilities.
51  * @best_parent_hw:	The most appropriate parent clock that fulfills the
64  * struct clk_duty - Struture encoding the duty cycle ratio of a clock
75  * struct clk_ops -  Callback operations for hardware clocks; these are to
76  * be provided by the clock implementation, and will be called by drivers
79  * @prepare:	Prepare the clock for enabling. This must not return until
80  *		the clock is fully prepared, and it's safe to call clk_enable.
81  *		This callback is intended to allow clock implementations to
85  * @unprepare:	Release the clock from its prepared state. This will typically
89  * @is_prepared: Queries the hardware to determine if the clock is prepared.
93  * @unprepare_unused: Unprepare the clock atomically.  Only called from
97  * @enable:	Enable the clock atomically. This must not return until the
98  *		clock is generating a valid clock signal, usable by consumer
102  * @disable:	Disable the clock atomically. Called with enable_lock held.
105  * @is_enabled:	Queries the hardware to determine if the clock is enabled.
109  * @disable_unused: Disable the clock atomically.  Only called from
114  * @save_context: Save the context of the clock in prepration for poweroff.
116  * @restore_context: Restore the context of the clock after a restoration
119  * @recalc_rate	Recalculate the rate of this clock, by querying hardware. The
122  *		Returns the calculated rate.  Optional, but recommended - if
123  *		this op is not set then clock rate will be initialized to 0.
126  *		supported by the clock. The parent rate is an input/output
130  *		actually supported by the clock, and optionally the parent clock
131  *		that should be used to provide the clock rate.
133  * @set_parent:	Change the input source of this clock; for clocks with multiple
138  *		Returns 0 on success, -EERROR otherwise.
140  * @get_parent:	Queries the hardware to determine the parent of a clock.  The
142  *		the parent clock.  This index can be applied to either the
145  *		index.  Currently only called when the clock is initialized by
150  * @set_rate:	Change the rate of this clock. The requested rate is specified
154  *		Returns 0 on success, -EERROR otherwise.
156  * @set_rate_and_parent: Change the rate and the parent of this clock. The
165  *		Returns 0 on success, -EERROR otherwise.
167  * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
170  *		Returns the calculated accuracy.  Optional - if	this op is not
171  *		set then clock accuracy will be initialized to parent accuracy
172  *		or 0 (perfect clock) if clock has no parent.
174  * @get_phase:	Queries the hardware to get the current phase of a clock.
175  *		Returned values are 0-359 degrees on success, negative
178  * @set_phase:	Shift the phase this clock signal in degrees specified
180  *		0-359. Return 0 on success, otherwise -EERROR.
183  *              of a clock. Returned values denominator cannot be 0 and must be
186  * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
189  *              and >= numerator) Return 0 on success, otherwise -EERROR.
191  * @init:	Perform platform-specific initialization magic.
192  *		This is not used by any of the basic clock types.
195  *		clock. It may also be used dynamic resource allocation is
196  *		required. It shall not used to deal with clock parameters,
198  *		Returns 0 on success, -EERROR otherwise.
202  * @debug_init:	Set up type-specific debugfs entries for this clock.  This
204  *		clock has been created.  The dentry pointer representing that
206  *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
211  * (prepare) contexts.  If enabling a clock requires code that might sleep,
212  * this must be done in clk_prepare.  Clock enable code that will never be
215  * Typically, drivers will call clk_prepare when a clock may be needed later
216  * (eg. when a device is opened), and clk_enable when the clock is actually
258  * struct clk_parent_data - clk parent information
260  * @fw_name: parent name local to provider registering clk
261  * @name: globally unique parent name (used as a fallback)
267 	const char		*name;  member
272  * struct clk_init_data - holds init data that's common to all clocks and is
273  * shared between the clock provider and the common clock framework.
275  * @name: clock name
276  * @ops: operations this clock supports
283  * @flags: framework-level hints and quirks
286 	const char		*name;  member
297  * struct clk_hw - handle for traversing from a struct clk to its corresponding
298  * hardware-specific structure.  struct clk_hw should be declared within struct
305  * @clk: pointer to the per-user struct clk instance that can be used to call
309  * with the common clock framework. This pointer will be set to NULL once
319  * DOC: Basic clock implementations common to many platforms
321  * Each basic clock hardware type is comprised of a structure describing the
322  * clock hardware, implementations of the relevant callbacks in struct clk_ops,
328  * struct clk_fixed_rate - fixed-rate clock
329  * @hw:		handle between common and hardware-specific interfaces
330  * @fixed_rate:	constant frequency of clock
331  * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
335  * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
349 		struct device_node *np, const char *name,
354 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
358  * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
360  * @dev: device that is registering this clock
361  * @name: name of this clock
362  * @parent_name: name of clock's parent
363  * @flags: framework-specific flags
364  * @fixed_rate: non-adjustable clock rate
366 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate)  \  argument
367 	__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
370  * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
371  * the clock framework
372  * @dev: device that is registering this clock
373  * @name: name of this clock
375  * @flags: framework-specific flags
376  * @fixed_rate: non-adjustable clock rate
378 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags,     \  argument
380 	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw),  \
383  * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
384  * the clock framework
385  * @dev: device that is registering this clock
386  * @name: name of this clock
388  * @flags: framework-specific flags
389  * @fixed_rate: non-adjustable clock rate
391 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags,   \  argument
393 	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL,	      \
397  * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
398  * the clock framework
399  * @dev: device that is registering this clock
400  * @name: name of this clock
401  * @parent_name: name of clock's parent
402  * @flags: framework-specific flags
403  * @fixed_rate: non-adjustable clock rate
404  * @fixed_accuracy: non-adjustable clock accuracy
406 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name,      \  argument
409 	__clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name),      \
413  * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
414  * clock with the clock framework
415  * @dev: device that is registering this clock
416  * @name: name of this clock
418  * @flags: framework-specific flags
419  * @fixed_rate: non-adjustable clock rate
420  * @fixed_accuracy: non-adjustable clock accuracy
422 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name,	      \  argument
424 	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw)   \
428  * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
429  * clock with the clock framework
430  * @dev: device that is registering this clock
431  * @name: name of this clock
432  * @parent_name: name of clock's parent
433  * @flags: framework-specific flags
434  * @fixed_rate: non-adjustable clock rate
435  * @fixed_accuracy: non-adjustable clock accuracy
437 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name,	      \  argument
439 	__clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL,	      \
449  * struct clk_gate - gating clock
451  * @hw:		handle between common and hardware-specific interfaces
454  * @flags:	hardware-specific flags
457  * Clock which can gate its output.  Implements .enable & .disable
460  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
461  *	enable the clock.  Setting this flag does the opposite: setting the bit
462  *	disable the clock and clearing it enables the clock
463  * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
464  *	of this register, and mask of gate bits are in higher 16-bit of this
465  *	register.  While setting the gate bits, higher 16-bit should also be
467  * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
487 		struct device_node *np, const char *name,
493 struct clk *clk_register_gate(struct device *dev, const char *name,
498  * clk_hw_register_gate - register a gate clock with the clock framework
499  * @dev: device that is registering this clock
500  * @name: name of this clock
501  * @parent_name: name of this clock's parent
502  * @flags: framework-specific flags for this clock
503  * @reg: register address to control gating of this clock
504  * @bit_idx: which bit in the register controls gating of this clock
505  * @clk_gate_flags: gate-specific flags for this clock
506  * @lock: shared register lock for this clock
508 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,     \  argument
510 	__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL,      \
514  * clk_hw_register_gate_parent_hw - register a gate clock with the clock
516  * @dev: device that is registering this clock
517  * @name: name of this clock
519  * @flags: framework-specific flags for this clock
520  * @reg: register address to control gating of this clock
521  * @bit_idx: which bit in the register controls gating of this clock
522  * @clk_gate_flags: gate-specific flags for this clock
523  * @lock: shared register lock for this clock
525 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg,      \  argument
527 	__clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw),        \
531  * clk_hw_register_gate_parent_data - register a gate clock with the clock
533  * @dev: device that is registering this clock
534  * @name: name of this clock
536  * @flags: framework-specific flags for this clock
537  * @reg: register address to control gating of this clock
538  * @bit_idx: which bit in the register controls gating of this clock
539  * @clk_gate_flags: gate-specific flags for this clock
540  * @lock: shared register lock for this clock
542 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg,  \  argument
544 	__clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
557  * struct clk_divider - adjustable divider clock
559  * @hw:		handle between common and hardware-specific interfaces
566  * Clock with an adjustable divider affecting its output frequency.  Implements
570  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
574  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
576  * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
579  *	zero divisor by not modifying their input clock
581  * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
582  *	of this register, and mask of divider bits are in higher 16-bit of this
583  *	register.  While setting the divider bits, higher 16-bit should also be
585  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
587  * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
588  *	not be changed by the clock framework.
589  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
592  * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
606 #define clk_div_mask(width)	((1 << (width)) - 1)
637 		struct device_node *np, const char *name,
642 struct clk *clk_register_divider_table(struct device *dev, const char *name,
648  * clk_register_divider - register a divider clock with the clock framework
649  * @dev: device registering this clock
650  * @name: name of this clock
651  * @parent_name: name of clock's parent
652  * @flags: framework-specific flags
656  * @clk_divider_flags: divider-specific flags for this clock
657  * @lock: shared register lock for this clock
659 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \  argument
661 	clk_register_divider_table((dev), (name), (parent_name), (flags),      \
665  * clk_hw_register_divider - register a divider clock with the clock framework
666  * @dev: device registering this clock
667  * @name: name of this clock
668  * @parent_name: name of clock's parent
669  * @flags: framework-specific flags
673  * @clk_divider_flags: divider-specific flags for this clock
674  * @lock: shared register lock for this clock
676 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift,    \  argument
678 	__clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL,   \
682  * clk_hw_register_divider_parent_hw - register a divider clock with the clock
684  * @dev: device registering this clock
685  * @name: name of this clock
687  * @flags: framework-specific flags
691  * @clk_divider_flags: divider-specific flags for this clock
692  * @lock: shared register lock for this clock
694 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg,   \  argument
697 	__clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw),     \
701  * clk_hw_register_divider_parent_data - register a divider clock with the clock
703  * @dev: device registering this clock
704  * @name: name of this clock
706  * @flags: framework-specific flags
710  * @clk_divider_flags: divider-specific flags for this clock
711  * @lock: shared register lock for this clock
713 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags,    \  argument
716 	__clk_hw_register_divider((dev), NULL, (name), NULL, NULL,	      \
720  * clk_hw_register_divider_table - register a table based divider clock with
721  * the clock framework
722  * @dev: device registering this clock
723  * @name: name of this clock
724  * @parent_name: name of clock's parent
725  * @flags: framework-specific flags
729  * @clk_divider_flags: divider-specific flags for this clock
731  * @lock: shared register lock for this clock
733 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg,     \  argument
736 	__clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL,   \
740  * clk_hw_register_divider_table_parent_hw - register a table based divider
741  * clock with the clock framework
742  * @dev: device registering this clock
743  * @name: name of this clock
745  * @flags: framework-specific flags
749  * @clk_divider_flags: divider-specific flags for this clock
751  * @lock: shared register lock for this clock
753 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags,  \  argument
757 	__clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw),     \
761  * clk_hw_register_divider_table_parent_data - register a table based divider
762  * clock with the clock framework
763  * @dev: device registering this clock
764  * @name: name of this clock
766  * @flags: framework-specific flags
770  * @clk_divider_flags: divider-specific flags for this clock
772  * @lock: shared register lock for this clock
774 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data,     \  argument
778 	__clk_hw_register_divider((dev), NULL, (name), NULL, NULL,	      \
787  * struct clk_mux - multiplexer clock
789  * @hw:		handle between common and hardware-specific interfaces
794  * @flags:	hardware-specific flags
797  * Clock with multiple selectable parents.  Implements .get_parent, .set_parent
801  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
802  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
803  * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
804  *	register, and mask of mux bits are in higher 16-bit of this register.
805  *	While setting the mux bits, higher 16-bit should also be updated to
807  * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
809  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
811  * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
838 		const char *name, u8 num_parents,
844 struct clk *clk_register_mux_table(struct device *dev, const char *name,
849 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg,    \  argument
851 	clk_register_mux_table((dev), (name), (parent_names), (num_parents),  \
852 			       (flags), (reg), (shift), BIT((width)) - 1,     \
854 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents,	      \  argument
857 	__clk_hw_register_mux((dev), NULL, (name), (num_parents),	      \
861 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \  argument
863 	__clk_hw_register_mux((dev), NULL, (name), (num_parents),	      \
865 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
867 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags,    \  argument
869 	__clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL,	      \
871 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
872 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents,  \  argument
875 	__clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
877 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
889  * struct clk_fixed_factor - fixed multiplier and divider clock
891  * @hw:		handle between common and hardware-specific interfaces
895  * Clock with a fixed multiplier and divider. The output frequency is the
896  * parent clock rate divided by div and multiplied by mult.
909 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
914 		const char *name, const char *parent_name, unsigned long flags,
919  * struct clk_fractional_divider - adjustable fractional divider clock
921  * @hw:		handle between common and hardware-specific interfaces
929  * Clock with adjustable fractional divider affecting its output frequency.
932  * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
936  * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
963 		const char *name, const char *parent_name, unsigned long flags,
967 		const char *name, const char *parent_name, unsigned long flags,
973  * struct clk_multiplier - adjustable multiplier clock
975  * @hw:		handle between common and hardware-specific interfaces
981  * Clock with an adjustable multiplier affecting its output frequency.
985  * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
987  *	zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
990  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
992  * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1014  * struct clk_composite - aggregate clock of mux, divider and gate clocks
1016  * @hw:		handle between common and hardware-specific interfaces
1017  * @mux_hw:	handle between composite and hardware-specific mux clock
1018  * @rate_hw:	handle between composite and hardware-specific rate clock
1019  * @gate_hw:	handle between composite and hardware-specific gate clock
1020  * @mux_ops:	clock ops for mux
1021  * @rate_ops:	clock ops for rate
1022  * @gate_ops:	clock ops for gate
1039 struct clk *clk_register_composite(struct device *dev, const char *name,
1045 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1052 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1059 		const char *name,
1107 struct clk *__clk_lookup(const char *name);
1122 	dst->clk = src->clk;  in __clk_hw_set_clk()
1123 	dst->core = src->core;  in __clk_hw_set_clk()
1147  * FIXME clock api without lock protection
1161 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)  argument
1167 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \  argument
1168 	static void __init name##_of_clk_init_driver(struct device_node *np) \
1173 	OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1178 		.name		= _name,			\
1187 		.name		= _name,				\
1201 		.name		= _name,				\
1210 		.name		= _name,				\
1221 		.name		= _name,			\
1230 		.name		= _name,			\
1239 		.name		= _name,			\
1248 		.name           = _name,		\
1357 	return ERR_PTR(-ENOENT);  in of_clk_src_simple_get()
1362 	return ERR_PTR(-ENOENT);  in of_clk_hw_simple_get()
1367 	return ERR_PTR(-ENOENT);  in of_clk_src_onecell_get()
1372 	return ERR_PTR(-ENOENT);  in of_clk_hw_onecell_get()