Lines Matching full:by
376 /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
378 /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
380 /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
384 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
386 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
388 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
398 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
400 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
402 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
404 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
406 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
408 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
410 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
412 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
414 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
425 /* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
427 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
429 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
431 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
433 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
435 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
439 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
443 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
445 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
447 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
449 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
451 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
453 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
455 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
457 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
459 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
473 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
479 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
481 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
485 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
491 /** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
509 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
513 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
515 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
517 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
519 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
521 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
523 /**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
525 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
527 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
529 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
531 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
533 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
537 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
543 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
545 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
569 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
571 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
573 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
575 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
577 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
579 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
581 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
587 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
589 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
591 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
593 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
599 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
601 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
603 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
605 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
607 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
609 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
611 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
613 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
615 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
617 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
619 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
621 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
623 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
625 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
627 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
629 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
631 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
633 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
637 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
639 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
641 /** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
643 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
645 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
649 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
653 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
655 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
657 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
659 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
661 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
663 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
665 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
667 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
669 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
671 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
673 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
675 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
677 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read…
679 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
681 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
683 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
687 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
691 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
695 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
713 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
715 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
717 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
719 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
721 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
723 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
725 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
727 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
729 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
731 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
733 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
735 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
737 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
742 * * VCO/pdiv defined by this clock object
743 * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
751 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
753 /** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider …
765 /** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
784 * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
787 * is controlled by sw using clk_enable/clk_disable on
793 /** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SO…
795 /** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SO…
811 /** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC…
829 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
831 /** Fixed 408MHz PLL for use by peripheral clocks */
835 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
837 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
840 * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
846 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
848 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
850 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
852 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
854 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
856 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
858 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
860 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
862 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
864 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain …