1 // SPDX-License-Identifier: GPL-2.0
90 	u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr;  in stm32_iwdg_start()  local
93 	dev_dbg(wdd->parent, "%s\n", __func__);  in stm32_iwdg_start()
95 	tout = clamp_t(unsigned int, wdd->timeout,  in stm32_iwdg_start()
96 		       wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);  in stm32_iwdg_start()
98 	presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);  in stm32_iwdg_start()
101 	presc = roundup_pow_of_two(presc);  in stm32_iwdg_start()
102 	iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;  in stm32_iwdg_start()
103 	iwdg_rlr = ((tout * wdt->rate) / presc) - 1;  in stm32_iwdg_start()
106 	reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);  in stm32_iwdg_start()
109 	reg_write(wdt->regs, IWDG_PR, iwdg_pr);  in stm32_iwdg_start()
110 	reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);  in stm32_iwdg_start()
111 	reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);  in stm32_iwdg_start()
114 	ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,  in stm32_iwdg_start()
118 		dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");  in stm32_iwdg_start()
123 	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);  in stm32_iwdg_start()
132 	dev_dbg(wdd->parent, "%s\n", __func__);  in stm32_iwdg_ping()
135 	reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);  in stm32_iwdg_ping()
143 	dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);  in stm32_iwdg_set_timeout()
145 	wdd->timeout = timeout;  in stm32_iwdg_set_timeout()
161 	struct device *dev = &pdev->dev;  in stm32_iwdg_clk_init()
164 	wdt->clk_lsi = devm_clk_get(dev, "lsi");  in stm32_iwdg_clk_init()
165 	if (IS_ERR(wdt->clk_lsi)) {  in stm32_iwdg_clk_init()
166 		dev_err(dev, "Unable to get lsi clock\n");  in stm32_iwdg_clk_init()
167 		return PTR_ERR(wdt->clk_lsi);  in stm32_iwdg_clk_init()
170 	/* optional peripheral clock */  in stm32_iwdg_clk_init()
171 	if (wdt->data->has_pclk) {  in stm32_iwdg_clk_init()
172 		wdt->clk_pclk = devm_clk_get(dev, "pclk");  in stm32_iwdg_clk_init()
173 		if (IS_ERR(wdt->clk_pclk)) {  in stm32_iwdg_clk_init()
174 			dev_err(dev, "Unable to get pclk clock\n");  in stm32_iwdg_clk_init()
175 			return PTR_ERR(wdt->clk_pclk);  in stm32_iwdg_clk_init()
178 		ret = clk_prepare_enable(wdt->clk_pclk);  in stm32_iwdg_clk_init()
180 			dev_err(dev, "Unable to prepare pclk clock\n");  in stm32_iwdg_clk_init()
185 					       wdt->clk_pclk);  in stm32_iwdg_clk_init()
190 	ret = clk_prepare_enable(wdt->clk_lsi);  in stm32_iwdg_clk_init()
192 		dev_err(dev, "Unable to prepare lsi clock\n");  in stm32_iwdg_clk_init()
196 				       wdt->clk_lsi);  in stm32_iwdg_clk_init()
200 	wdt->rate = clk_get_rate(wdt->clk_lsi);  in stm32_iwdg_clk_init()
220 	{ .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
221 	{ .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
228 	struct device *dev = &pdev->dev;  in stm32_iwdg_probe()
235 		return -ENOMEM;  in stm32_iwdg_probe()
237 	wdt->data = of_device_get_match_data(&pdev->dev);  in stm32_iwdg_probe()
238 	if (!wdt->data)  in stm32_iwdg_probe()
239 		return -ENODEV;  in stm32_iwdg_probe()
242 	wdt->regs = devm_platform_ioremap_resource(pdev, 0);  in stm32_iwdg_probe()
243 	if (IS_ERR(wdt->regs)) {  in stm32_iwdg_probe()
245 		return PTR_ERR(wdt->regs);  in stm32_iwdg_probe()
253 	wdd = &wdt->wdd;  in stm32_iwdg_probe()
254 	wdd->parent = dev;  in stm32_iwdg_probe()
255 	wdd->info = &stm32_iwdg_info;  in stm32_iwdg_probe()
256 	wdd->ops = &stm32_iwdg_ops;  in stm32_iwdg_probe()
257 	wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);  in stm32_iwdg_probe()
258 	wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *  in stm32_iwdg_probe()
259 				    1000) / wdt->rate;  in stm32_iwdg_probe()
267 	 * (Means U-Boot/bootloaders leaves the watchdog running)  in stm32_iwdg_probe()
280 		set_bit(WDOG_HW_RUNNING, &wdd->status);  in stm32_iwdg_probe()