3  * Support for the Tundra TSI148 VME-PCI Bridge Chip
75 static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,  in tsi148_DMA_irqhandler()  argument
81 		wake_up(&bridge->dma_queue[0]);  in tsi148_DMA_irqhandler()
85 		wake_up(&bridge->dma_queue[1]);  in tsi148_DMA_irqhandler()
95 static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)  in tsi148_LM_irqhandler()  argument
103 			bridge->lm_callback[i](bridge->lm_data[i]);  in tsi148_LM_irqhandler()
121 	struct tsi148_driver *bridge;  in tsi148_MB_irqhandler()  local
123 	bridge = tsi148_bridge->driver_priv;  in tsi148_MB_irqhandler()
127 			val = ioread32be(bridge->base +	TSI148_GCSR_MBOX[i]);  in tsi148_MB_irqhandler()
142 	struct tsi148_driver *bridge;  in tsi148_PERR_irqhandler()  local
144 	bridge = tsi148_bridge->driver_priv;  in tsi148_PERR_irqhandler()
148 		ioread32be(bridge->base + TSI148_LCSR_EDPAU),  in tsi148_PERR_irqhandler()
149 		ioread32be(bridge->base + TSI148_LCSR_EDPAL),  in tsi148_PERR_irqhandler()
150 		ioread32be(bridge->base + TSI148_LCSR_EDPAT));  in tsi148_PERR_irqhandler()
154 		ioread32be(bridge->base + TSI148_LCSR_EDPXA),  in tsi148_PERR_irqhandler()
155 		ioread32be(bridge->base + TSI148_LCSR_EDPXS));  in tsi148_PERR_irqhandler()
157 	iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);  in tsi148_PERR_irqhandler()
171 	struct tsi148_driver *bridge;  in tsi148_VERR_irqhandler()  local
173 	bridge = tsi148_bridge->driver_priv;  in tsi148_VERR_irqhandler()
175 	error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);  in tsi148_VERR_irqhandler()
176 	error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);  in tsi148_VERR_irqhandler()
177 	error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);  in tsi148_VERR_irqhandler()
196 	iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);  in tsi148_VERR_irqhandler()
204 static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)  in tsi148_IACK_irqhandler()  argument
206 	wake_up(&bridge->iack_queue);  in tsi148_IACK_irqhandler()
218 	struct tsi148_driver *bridge;  in tsi148_VIRQ_irqhandler()  local
220 	bridge = tsi148_bridge->driver_priv;  in tsi148_VIRQ_irqhandler()
229 			vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);  in tsi148_VIRQ_irqhandler()
248 	struct tsi148_driver *bridge;  in tsi148_irqhandler()  local
252 	bridge = tsi148_bridge->driver_priv;  in tsi148_irqhandler()
255 	enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_irqhandler()
256 	stat = ioread32be(bridge->base + TSI148_LCSR_INTS);  in tsi148_irqhandler()
267 		serviced |= tsi148_DMA_irqhandler(bridge, stat);  in tsi148_irqhandler()
272 		serviced |= tsi148_LM_irqhandler(bridge, stat);  in tsi148_irqhandler()
289 		serviced |= tsi148_IACK_irqhandler(bridge);  in tsi148_irqhandler()
299 	iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);  in tsi148_irqhandler()
309 	struct tsi148_driver *bridge;  in tsi148_irq_init()  local
313 	bridge = tsi148_bridge->driver_priv;  in tsi148_irq_init()
359 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_init()
360 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_init()
368 	struct tsi148_driver *bridge = tsi148_bridge->driver_priv;  in tsi148_irq_exit()  local
371 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_exit()
372 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_exit()
375 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);  in tsi148_irq_exit()
384 static int tsi148_iack_received(struct tsi148_driver *bridge)  in tsi148_iack_received()  argument
388 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);  in tsi148_iack_received()
404 	struct tsi148_driver *bridge;  in tsi148_irq_set()  local
406 	bridge = tsi148_bridge->driver_priv;  in tsi148_irq_set()
410 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
412 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
414 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
416 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
423 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
425 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_irq_set()
427 		tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
429 		iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_irq_set()
441 	struct tsi148_driver *bridge;  in tsi148_irq_generate()  local
443 	bridge = tsi148_bridge->driver_priv;  in tsi148_irq_generate()
445 	mutex_lock(&bridge->vme_int);  in tsi148_irq_generate()
448 	tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
453 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
457 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);  in tsi148_irq_generate()
460 	wait_event_interruptible(bridge->iack_queue,  in tsi148_irq_generate()
461 		tsi148_iack_received(bridge));  in tsi148_irq_generate()
463 	mutex_unlock(&bridge->vme_int);  in tsi148_irq_generate()
482 	struct tsi148_driver *bridge;  in tsi148_slave_set()  local
485 	bridge = tsi148_bridge->driver_priv;  in tsi148_slave_set()
539 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
542 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
546 	iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
548 	iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
550 	iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
552 	iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
554 	iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
556 	iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
601 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
607 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_set()
625 	struct tsi148_driver *bridge;  in tsi148_slave_get()  local
627 	bridge = image->parent->driver_priv;  in tsi148_slave_get()
632 	ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
635 	vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
637 	vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
639 	vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
641 	vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
643 	pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
645 	pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +  in tsi148_slave_get()
819 	struct tsi148_driver *bridge;  in tsi148_master_set()  local
825 	bridge = tsi148_bridge->driver_priv;  in tsi148_master_set()
903 	temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
906 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1008 	iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1010 	iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1012 	iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1014 	iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1016 	iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1018 	iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1022 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1028 	iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_set()
1059 	struct tsi148_driver *bridge;  in __tsi148_master_get()  local
1061 	bridge = image->parent->driver_priv;  in __tsi148_master_get()
1065 	ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1068 	pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1070 	pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1072 	pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1074 	pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1076 	vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1078 	vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in __tsi148_master_get()
1205 	 * On the other hand, the bridge itself assures that the maximum data  in tsi148_master_read()
1273 	struct tsi148_driver *bridge;  in tsi148_master_write()  local
1277 	bridge = tsi148_bridge->driver_priv;  in tsi148_master_write()
1342 		ioread16(bridge->flush_image->kern_base + 0x7F000);  in tsi148_master_write()
1371 	struct tsi148_driver *bridge;  in tsi148_master_rmw()  local
1373 	bridge = image->parent->driver_priv;  in tsi148_master_rmw()
1379 	mutex_lock(&bridge->vme_rmw);  in tsi148_master_rmw()
1384 	pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_rmw()
1386 	pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +  in tsi148_master_rmw()
1393 	iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);  in tsi148_master_rmw()
1394 	iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);  in tsi148_master_rmw()
1395 	iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);  in tsi148_master_rmw()
1396 	iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);  in tsi148_master_rmw()
1397 	iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);  in tsi148_master_rmw()
1400 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1402 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1408 	tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1410 	iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);  in tsi148_master_rmw()
1414 	mutex_unlock(&bridge->vme_rmw);  in tsi148_master_rmw()
1788 	struct tsi148_driver *bridge;  in tsi148_dma_busy()  local
1790 	bridge = tsi148_bridge->driver_priv;  in tsi148_dma_busy()
1792 	tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +  in tsi148_dma_busy()
1815 	struct tsi148_driver *bridge;  in tsi148_dma_list_exec()  local
1821 	bridge = tsi148_bridge->driver_priv;  in tsi148_dma_list_exec()
1848 	iowrite32be(bus_addr_high, bridge->base +  in tsi148_dma_list_exec()
1850 	iowrite32be(bus_addr_low, bridge->base +  in tsi148_dma_list_exec()
1853 	dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +  in tsi148_dma_list_exec()
1857 	iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +  in tsi148_dma_list_exec()
1860 	retval = wait_event_interruptible(bridge->dma_queue[channel],  in tsi148_dma_list_exec()
1864 		iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base +  in tsi148_dma_list_exec()
1867 		wait_event(bridge->dma_queue[channel],  in tsi148_dma_list_exec()
1877 	val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +  in tsi148_dma_list_exec()
1932 	struct tsi148_driver *bridge;  in tsi148_lm_set()  local
1936 	bridge = tsi148_bridge->driver_priv;  in tsi148_lm_set()
1942 		if (bridge->lm_callback[i]) {  in tsi148_lm_set()
1981 	iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);  in tsi148_lm_set()
1982 	iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);  in tsi148_lm_set()
1983 	iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_set()
1997 	struct tsi148_driver *bridge;  in tsi148_lm_get()  local
1999 	bridge = lm->parent->driver_priv;  in tsi148_lm_get()
2003 	lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);  in tsi148_lm_get()
2004 	lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);  in tsi148_lm_get()
2005 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_get()
2049 	struct tsi148_driver *bridge;  in tsi148_lm_attach()  local
2053 	bridge = tsi148_bridge->driver_priv;  in tsi148_lm_attach()
2058 	lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_attach()
2067 	if (bridge->lm_callback[monitor]) {  in tsi148_lm_attach()
2074 	bridge->lm_callback[monitor] = callback;  in tsi148_lm_attach()
2075 	bridge->lm_data[monitor] = data;  in tsi148_lm_attach()
2078 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_attach()
2080 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_attach()
2082 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_attach()
2084 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_attach()
2089 		iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_attach()
2103 	struct tsi148_driver *bridge;  in tsi148_lm_detach()  local
2105 	bridge = lm->parent->driver_priv;  in tsi148_lm_detach()
2110 	lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_detach()
2112 	iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);  in tsi148_lm_detach()
2114 	tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_detach()
2116 	iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);  in tsi148_lm_detach()
2119 		 bridge->base + TSI148_LCSR_INTC);  in tsi148_lm_detach()
2122 	bridge->lm_callback[monitor] = NULL;  in tsi148_lm_detach()
2123 	bridge->lm_data[monitor] = NULL;  in tsi148_lm_detach()
2128 		tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_detach()
2130 		iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);  in tsi148_lm_detach()
2144 	struct tsi148_driver *bridge;  in tsi148_slot_get()  local
2146 	bridge = tsi148_bridge->driver_priv;  in tsi148_slot_get()
2149 		slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);  in tsi148_slot_get()
2197 	struct tsi148_driver *bridge;  in tsi148_crcsr_init()  local
2199 	bridge = tsi148_bridge->driver_priv;  in tsi148_crcsr_init()
2202 	bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE,  in tsi148_crcsr_init()
2203 						     &bridge->crcsr_bus);  in tsi148_crcsr_init()
2204 	if (!bridge->crcsr_kernel) {  in tsi148_crcsr_init()
2210 	reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);  in tsi148_crcsr_init()
2212 	iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);  in tsi148_crcsr_init()
2213 	iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);  in tsi148_crcsr_init()
2216 	cbar = ioread32be(bridge->base + TSI148_CBAR);  in tsi148_crcsr_init()
2224 		iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);  in tsi148_crcsr_init()
2228 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_init()
2234 			bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_init()
2242 		retval = tsi148_master_set(bridge->flush_image, 1,  in tsi148_crcsr_init()
2258 	struct tsi148_driver *bridge;  in tsi148_crcsr_exit()  local
2260 	bridge = tsi148_bridge->driver_priv;  in tsi148_crcsr_exit()
2263 	crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_exit()
2265 		bridge->base + TSI148_LCSR_CRAT);  in tsi148_crcsr_exit()
2268 	iowrite32be(0, bridge->base + TSI148_LCSR_CROU);  in tsi148_crcsr_exit()
2269 	iowrite32be(0, bridge->base + TSI148_LCSR_CROL);  in tsi148_crcsr_exit()
2271 	pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,  in tsi148_crcsr_exit()
2272 		bridge->crcsr_bus);  in tsi148_crcsr_exit()
2287 	/* If we want to support more than one of each bridge, we need to  in tsi148_probe()
2572 	struct tsi148_driver *bridge;  in tsi148_remove()  local
2575 	bridge = tsi148_bridge->driver_priv;  in tsi148_remove()
2584 		iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +  in tsi148_remove()
2586 		iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +  in tsi148_remove()
2593 	iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);  in tsi148_remove()
2598 	iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);  in tsi148_remove()
2603 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);  in tsi148_remove()
2604 	iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);  in tsi148_remove()
2605 	iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);  in tsi148_remove()
2610 	if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)  in tsi148_remove()
2611 		iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);  in tsi148_remove()
2616 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);  in tsi148_remove()
2617 	iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);  in tsi148_remove()
2647 	iounmap(bridge->base);  in tsi148_remove()
2666 MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");