Lines Matching refs:masters

65 	struct fake_master_window masters[FAKE_MAX_MASTER];  member
317 bridge->masters[i].enabled = enabled; in fake_master_set()
318 bridge->masters[i].vme_base = vme_base; in fake_master_set()
319 bridge->masters[i].size = size; in fake_master_set()
320 bridge->masters[i].aspace = aspace; in fake_master_set()
321 bridge->masters[i].cycle = cycle; in fake_master_set()
322 bridge->masters[i].dwidth = dwidth; in fake_master_set()
349 *enabled = bridge->masters[i].enabled; in __fake_master_get()
350 *vme_base = bridge->masters[i].vme_base; in __fake_master_get()
351 *size = bridge->masters[i].size; in __fake_master_get()
352 *aspace = bridge->masters[i].aspace; in __fake_master_get()
353 *cycle = bridge->masters[i].cycle; in __fake_master_get()
354 *dwidth = bridge->masters[i].dwidth; in __fake_master_get()
534 addr = (unsigned long long)priv->masters[i].vme_base + offset; in fake_master_read()
535 aspace = priv->masters[i].aspace; in fake_master_read()
536 cycle = priv->masters[i].cycle; in fake_master_read()
537 dwidth = priv->masters[i].dwidth; in fake_master_read()
727 addr = bridge->masters[i].vme_base + offset; in fake_master_write()
728 aspace = bridge->masters[i].aspace; in fake_master_write()
729 cycle = bridge->masters[i].cycle; in fake_master_write()
730 dwidth = bridge->masters[i].dwidth; in fake_master_write()
824 base = bridge->masters[i].vme_base; in fake_master_rmw()
825 aspace = bridge->masters[i].aspace; in fake_master_rmw()
826 cycle = bridge->masters[i].cycle; in fake_master_rmw()
1262 bridge->masters[i].enabled = 0; in fake_exit()