Lines Matching refs:dwidth
58 u32 dwidth; member
253 u32 aspace, u32 cycle, u32 dwidth) in fake_master_set() argument
284 switch (dwidth) { in fake_master_set()
322 bridge->masters[i].dwidth = dwidth; in fake_master_set()
340 u32 *aspace, u32 *cycle, u32 *dwidth) in __fake_master_get() argument
354 *dwidth = bridge->masters[i].dwidth; in __fake_master_get()
362 u32 *aspace, u32 *cycle, u32 *dwidth) in fake_master_get() argument
369 cycle, dwidth); in fake_master_get()
520 u32 aspace, cycle, dwidth; in fake_master_read() local
537 dwidth = priv->masters[i].dwidth; in fake_master_read()
555 if ((dwidth == VME_D16) || (dwidth == VME_D32)) { in fake_master_read()
570 if (dwidth == VME_D32) { in fake_master_read()
577 } else if (dwidth == VME_D16) { in fake_master_read()
584 } else if (dwidth == VME_D8) { in fake_master_read()
594 if ((dwidth == VME_D16) || (dwidth == VME_D32)) { in fake_master_read()
712 u32 aspace, cycle, dwidth; in fake_master_write() local
730 dwidth = bridge->masters[i].dwidth; in fake_master_write()
744 if ((dwidth == VME_D16) || (dwidth == VME_D32)) { in fake_master_write()
759 if (dwidth == VME_D32) { in fake_master_write()
766 } else if (dwidth == VME_D16) { in fake_master_write()
773 } else if (dwidth == VME_D8) { in fake_master_write()
783 if ((dwidth == VME_D16) || (dwidth == VME_D32)) { in fake_master_write()