Lines Matching +full:0 +full:x00c00000
21 #define PCI_VENDOR_ID_TUNDRA 0x10e3
25 #define PCI_DEVICE_ID_TUNDRA_CA91C142 0x0000
72 #define CA91CX42_PCI_ID 0x000
73 #define CA91CX42_PCI_CSR 0x004
74 #define CA91CX42_PCI_CLASS 0x008
75 #define CA91CX42_PCI_MISC0 0x00C
76 #define CA91CX42_PCI_BS 0x010
77 #define CA91CX42_PCI_MISC1 0x03C
79 #define LSI0_CTL 0x0100
80 #define LSI0_BS 0x0104
81 #define LSI0_BD 0x0108
82 #define LSI0_TO 0x010C
84 #define LSI1_CTL 0x0114
85 #define LSI1_BS 0x0118
86 #define LSI1_BD 0x011C
87 #define LSI1_TO 0x0120
89 #define LSI2_CTL 0x0128
90 #define LSI2_BS 0x012C
91 #define LSI2_BD 0x0130
92 #define LSI2_TO 0x0134
94 #define LSI3_CTL 0x013C
95 #define LSI3_BS 0x0140
96 #define LSI3_BD 0x0144
97 #define LSI3_TO 0x0148
99 #define LSI4_CTL 0x01A0
100 #define LSI4_BS 0x01A4
101 #define LSI4_BD 0x01A8
102 #define LSI4_TO 0x01AC
104 #define LSI5_CTL 0x01B4
105 #define LSI5_BS 0x01B8
106 #define LSI5_BD 0x01BC
107 #define LSI5_TO 0x01C0
109 #define LSI6_CTL 0x01C8
110 #define LSI6_BS 0x01CC
111 #define LSI6_BD 0x01D0
112 #define LSI6_TO 0x01D4
114 #define LSI7_CTL 0x01DC
115 #define LSI7_BS 0x01E0
116 #define LSI7_BD 0x01E4
117 #define LSI7_TO 0x01E8
131 #define SCYC_CTL 0x0170
132 #define SCYC_ADDR 0x0174
133 #define SCYC_EN 0x0178
134 #define SCYC_CMP 0x017C
135 #define SCYC_SWP 0x0180
136 #define LMISC 0x0184
137 #define SLSI 0x0188
138 #define L_CMDERR 0x018C
139 #define LAERR 0x0190
141 #define DCTL 0x0200
142 #define DTBC 0x0204
143 #define DLA 0x0208
144 #define DVA 0x0210
145 #define DCPP 0x0218
146 #define DGCS 0x0220
147 #define D_LLUE 0x0224
149 #define LINT_EN 0x0300
150 #define LINT_STAT 0x0304
151 #define LINT_MAP0 0x0308
152 #define LINT_MAP1 0x030C
153 #define VINT_EN 0x0310
154 #define VINT_STAT 0x0314
155 #define VINT_MAP0 0x0318
156 #define VINT_MAP1 0x031C
157 #define STATID 0x0320
159 #define V1_STATID 0x0324
160 #define V2_STATID 0x0328
161 #define V3_STATID 0x032C
162 #define V4_STATID 0x0330
163 #define V5_STATID 0x0334
164 #define V6_STATID 0x0338
165 #define V7_STATID 0x033C
167 static const int CA91CX42_V_STATID[8] = { 0, V1_STATID, V2_STATID, V3_STATID,
171 #define LINT_MAP2 0x0340
172 #define VINT_MAP2 0x0344
174 #define MBOX0 0x0348
175 #define MBOX1 0x034C
176 #define MBOX2 0x0350
177 #define MBOX3 0x0354
178 #define SEMA0 0x0358
179 #define SEMA1 0x035C
181 #define MAST_CTL 0x0400
182 #define MISC_CTL 0x0404
183 #define MISC_STAT 0x0408
184 #define USER_AM 0x040C
186 #define VSI0_CTL 0x0F00
187 #define VSI0_BS 0x0F04
188 #define VSI0_BD 0x0F08
189 #define VSI0_TO 0x0F0C
191 #define VSI1_CTL 0x0F14
192 #define VSI1_BS 0x0F18
193 #define VSI1_BD 0x0F1C
194 #define VSI1_TO 0x0F20
196 #define VSI2_CTL 0x0F28
197 #define VSI2_BS 0x0F2C
198 #define VSI2_BD 0x0F30
199 #define VSI2_TO 0x0F34
201 #define VSI3_CTL 0x0F3C
202 #define VSI3_BS 0x0F40
203 #define VSI3_BD 0x0F44
204 #define VSI3_TO 0x0F48
206 #define LM_CTL 0x0F64
207 #define LM_BS 0x0F68
209 #define VRAI_CTL 0x0F70
211 #define VRAI_BS 0x0F74
212 #define VCSR_CTL 0x0F80
213 #define VCSR_TO 0x0F84
214 #define V_AMERR 0x0F88
215 #define VAERR 0x0F8C
217 #define VSI4_CTL 0x0F90
218 #define VSI4_BS 0x0F94
219 #define VSI4_BD 0x0F98
220 #define VSI4_TO 0x0F9C
222 #define VSI5_CTL 0x0FA4
223 #define VSI5_BS 0x0FA8
224 #define VSI5_BD 0x0FAC
225 #define VSI5_TO 0x0FB0
227 #define VSI6_CTL 0x0FB8
228 #define VSI6_BS 0x0FBC
229 #define VSI6_BD 0x0FC0
230 #define VSI6_TO 0x0FC4
232 #define VSI7_CTL 0x0FCC
233 #define VSI7_BS 0x0FD0
234 #define VSI7_BD 0x0FD4
235 #define VSI7_TO 0x0FD8
249 #define VCSR_CLR 0x0FF4
250 #define VCSR_SET 0x0FF8
251 #define VCSR_BS 0x0FFC
257 #define CA91CX42_BM_PCI_CLASS_BASE 0xFF000000
259 #define CA91CX42_BM_PCI_CLASS_SUB 0x00FF0000
261 #define CA91CX42_BM_PCI_CLASS_PROG 0x0000FF00
263 #define CA91CX42_BM_PCI_CLASS_RID 0x000000FF
264 #define CA91CX42_OF_PCI_CLASS_RID 0
266 #define CA91CX42_OF_PCI_CLASS_RID_UNIVERSE_I 0
273 #define CA91CX42_BM_PCI_MISC0_BISTC 0x80000000
274 #define CA91CX42_BM_PCI_MISC0_SBIST 0x60000000
275 #define CA91CX42_BM_PCI_MISC0_CCODE 0x0F000000
276 #define CA91CX42_BM_PCI_MISC0_MFUNCT 0x00800000
277 #define CA91CX42_BM_PCI_MISC0_LAYOUT 0x007F0000
278 #define CA91CX42_BM_PCI_MISC0_LTIMER 0x0000FF00
290 #define CA91CX42_LSI_CTL_VDW_D8 0
296 #define CA91CX42_LSI_CTL_VAS_A16 0
304 #define CA91CX42_LSI_CTL_PGM_DATA 0
308 #define CA91CX42_LSI_CTL_SUPER_NPRIV 0
314 #define CA91CX42_LSI_CTL_LAS (1<<0)
320 #define CA91CX42_SCYC_CTL_LAS_PCIMEM 0
323 #define CA91CX42_SCYC_CTL_CYC_M (3<<0)
324 #define CA91CX42_SCYC_CTL_CYC_RMW (1<<0)
331 #define CA91CX42_BM_LMISC_CRT 0xF0000000
333 #define CA91CX42_BM_LMISC_CWT 0x0F000000
340 #define CA91CX42_BM_SLSI_EN 0x80000000
341 #define CA91CX42_BM_SLSI_PWEN 0x40000000
342 #define CA91CX42_BM_SLSI_VDW 0x00F00000
344 #define CA91CX42_BM_SLSI_PGM 0x0000F000
346 #define CA91CX42_BM_SLSI_SUPER 0x00000F00
348 #define CA91CX42_BM_SLSI_BS 0x000000F6
350 #define CA91CX42_BM_SLSI_LAS 0x00000003
351 #define CA91CX42_OF_SLSI_LAS 0
352 #define CA91CX42_BM_SLSI_RESERVED 0x3F0F0000
360 #define CA91CX42_DCTL_VDW_D8 0
366 #define CA91CX42_DCTL_VAS_A16 0
373 #define CA91CX42_DCTL_PGM_DATA 0
377 #define CA91CX42_DCTL_SUPER_NPRIV 0
388 #define CA91CX42_DCPP_M 0xf
389 #define CA91CX42_DCPP_NULL (1<<0)
402 #define CA91CX42_DGCS_VOFF_M (0xf<<16)
416 #define CA91CX42_DGCS_INT_PERR (1<<0)
422 #define CA91CX42_LINT_LM3 0x00800000
423 #define CA91CX42_LINT_LM2 0x00400000
424 #define CA91CX42_LINT_LM1 0x00200000
425 #define CA91CX42_LINT_LM0 0x00100000
426 #define CA91CX42_LINT_MBOX3 0x00080000
427 #define CA91CX42_LINT_MBOX2 0x00040000
428 #define CA91CX42_LINT_MBOX1 0x00020000
429 #define CA91CX42_LINT_MBOX0 0x00010000
430 #define CA91CX42_LINT_ACFAIL 0x00008000
431 #define CA91CX42_LINT_SYSFAIL 0x00004000
432 #define CA91CX42_LINT_SW_INT 0x00002000
433 #define CA91CX42_LINT_SW_IACK 0x00001000
435 #define CA91CX42_LINT_VERR 0x00000400
436 #define CA91CX42_LINT_LERR 0x00000200
437 #define CA91CX42_LINT_DMA 0x00000100
438 #define CA91CX42_LINT_VIRQ7 0x00000080
439 #define CA91CX42_LINT_VIRQ6 0x00000040
440 #define CA91CX42_LINT_VIRQ5 0x00000020
441 #define CA91CX42_LINT_VIRQ4 0x00000010
442 #define CA91CX42_LINT_VIRQ3 0x00000008
443 #define CA91CX42_LINT_VIRQ2 0x00000004
444 #define CA91CX42_LINT_VIRQ1 0x00000002
445 #define CA91CX42_LINT_VOWN 0x00000001
447 static const int CA91CX42_LINT_VIRQ[] = { 0, CA91CX42_LINT_VIRQ1,
452 #define CA91CX42_LINT_MBOX 0x000F0000
461 #define CA91CX42_BM_MAST_CTL_MAXRTRY 0xF0000000
463 #define CA91CX42_BM_MAST_CTL_PWON 0x0F000000
465 #define CA91CX42_BM_MAST_CTL_VRL 0x00C00000
467 #define CA91CX42_BM_MAST_CTL_VRM 0x00200000
468 #define CA91CX42_BM_MAST_CTL_VREL 0x00100000
469 #define CA91CX42_BM_MAST_CTL_VOWN 0x00080000
470 #define CA91CX42_BM_MAST_CTL_VOWN_ACK 0x00040000
471 #define CA91CX42_BM_MAST_CTL_PABS 0x00001000
472 #define CA91CX42_BM_MAST_CTL_BUS_NO 0x0000000F
473 #define CA91CX42_OF_MAST_CTL_BUS_NO 0
479 #define CA91CX42_MISC_CTL_VBTO 0xF0000000
480 #define CA91CX42_MISC_CTL_VARB 0x04000000
481 #define CA91CX42_MISC_CTL_VARBTO 0x03000000
482 #define CA91CX42_MISC_CTL_SW_LRST 0x00800000
483 #define CA91CX42_MISC_CTL_SW_SRST 0x00400000
484 #define CA91CX42_MISC_CTL_BI 0x00100000
485 #define CA91CX42_MISC_CTL_ENGBI 0x00080000
486 #define CA91CX42_MISC_CTL_RESCIND 0x00040000
487 #define CA91CX42_MISC_CTL_SYSCON 0x00020000
488 #define CA91CX42_MISC_CTL_V64AUTO 0x00010000
489 #define CA91CX42_MISC_CTL_RESERVED 0x0820FFFF
498 #define CA91CX42_BM_MISC_STAT_ENDIAN 0x80000000
499 #define CA91CX42_BM_MISC_STAT_LCLSIZE 0x40000000
500 #define CA91CX42_BM_MISC_STAT_DY4AUTO 0x08000000
501 #define CA91CX42_BM_MISC_STAT_MYBBSY 0x00200000
502 #define CA91CX42_BM_MISC_STAT_DY4DONE 0x00080000
503 #define CA91CX42_BM_MISC_STAT_TXFE 0x00040000
504 #define CA91CX42_BM_MISC_STAT_RXFE 0x00020000
505 #define CA91CX42_BM_MISC_STAT_DY4AUTOID 0x0000FF00
525 #define CA91CX42_VSI_CTL_VAS_A16 0
534 #define CA91CX42_VSI_CTL_LAS_M (3<<0)
535 #define CA91CX42_VSI_CTL_LAS_PCI_MS 0
536 #define CA91CX42_VSI_CTL_LAS_PCI_IO (1<<0)
548 #define CA91CX42_LM_CTL_AS_A16 0
556 #define CA91CX42_BM_VRAI_CTL_EN 0x80000000
557 #define CA91CX42_BM_VRAI_CTL_PGM 0x00C00000
559 #define CA91CX42_BM_VRAI_CTL_SUPER 0x00300000
561 #define CA91CX42_BM_VRAI_CTL_VAS 0x00030000
569 #define CA91CX42_VCSR_CTL_LAS_M (3<<0)
570 #define CA91CX42_VCSR_CTL_LAS_PCI_MS 0
571 #define CA91CX42_VCSR_CTL_LAS_PCI_IO (1<<0)
577 #define CA91CX42_VCSR_BS_SLOT_M (0x1F<<27)