345 	viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);  in load_lcd_scaling()
376 			viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);  in load_lcd_scaling()
388 		viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);  in load_lcd_scaling()
420 			viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);  in load_lcd_scaling()
432 		viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);  in load_lcd_scaling()
519 			viafb_write_reg_mask(CR99, VIACR, 0x08,  in lcd_patch_skew()
585 		viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);  in viafb_lcd_set_mode()
608 		viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);  in integrated_lvds_disable()
611 		viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);  in integrated_lvds_disable()
617 		viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);  in integrated_lvds_disable()
620 		viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);  in integrated_lvds_disable()
627 			viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);  in integrated_lvds_disable()
633 			viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);  in integrated_lvds_disable()
639 			viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);  in integrated_lvds_disable()
652 		viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);  in integrated_lvds_enable()
654 		viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);  in integrated_lvds_enable()
661 		viafb_write_reg_mask(CR91, VIACR, 0, BIT0);  in integrated_lvds_enable()
663 		viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);  in integrated_lvds_enable()
665 		viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);  in integrated_lvds_enable()
670 		viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);  in integrated_lvds_enable()
672 		viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);  in integrated_lvds_enable()
674 		viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);  in integrated_lvds_enable()
682 			viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);  in integrated_lvds_enable()
688 			viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);  in integrated_lvds_enable()
694 			viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);  in integrated_lvds_enable()
706 		viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);  in viafb_lcd_disable()
727 		viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);  in viafb_lcd_disable()
729 		viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);  in viafb_lcd_disable()
733 	viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);  in viafb_lcd_disable()
735 	viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);  in viafb_lcd_disable()
745 			viafb_write_reg_mask(CR97, VIACR, 0x84,  in set_lcd_output_path()
760 	viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);  in viafb_lcd_enable()
761 	viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);  in viafb_lcd_enable()
771 		viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);  in viafb_lcd_enable()
793 		viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);  in viafb_lcd_enable()
795 		viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);  in viafb_lcd_enable()
797 		viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);  in viafb_lcd_enable()
806 	viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);  in lcd_powersequence_off()
811 		viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);  in lcd_powersequence_off()
816 	viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);  in lcd_powersequence_off()
824 	viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);  in lcd_powersequence_on()
827 	viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);  in lcd_powersequence_on()
832 		viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);  in lcd_powersequence_on()
848 	viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);  in fill_lcd_format()