Lines Matching +full:0 +full:x43000000
120 #define REG_1 0x000118
121 #define REG_2 0x000480
122 #define REG_3 0x0004a0
123 #define REG_4 0x000600
124 #define REG_6 0x000800
125 #define REG_7 0x000804
126 #define REG_8 0x000820
127 #define REG_9 0x000a04
128 #define REG_10 0x018000
129 #define REG_11 0x018004
130 #define REG_12 0x01800c
131 #define REG_13 0x018018
132 #define REG_14 0x01801c
133 #define REG_15 0x200000
134 #define REG_15b0 0x200000
135 #define REG_16b1 0x200005
136 #define REG_16b3 0x200007
137 #define REG_21 0x200218
138 #define REG_22 0x0005a0
139 #define REG_23 0x0005c0
140 #define REG_24 0x000808
141 #define REG_25 0x000b00
142 #define REG_26 0x200118
143 #define REG_27 0x200308
144 #define REG_32 0x21003c
145 #define REG_33 0x210040
146 #define REG_34 0x200008
147 #define REG_35 0x018010
148 #define REG_38 0x210020
149 #define REG_39 0x210120
150 #define REG_40 0x210130
151 #define REG_42 0x210028
152 #define REG_43 0x21002c
153 #define REG_44 0x210030
154 #define REG_45 0x210034
167 # define DEBUG_OFF() debug_on=0
170 printk(KERN_DEBUG "%30s: WRITE_BYTE(0x%06x) = 0x%02x (old=0x%02x)\n", \
172 gsc_writeb((value),(fb)->info.fix.mmio_start + (reg)); } while (0)
174 printk(KERN_DEBUG "%30s: WRITE_WORD(0x%06x) = 0x%08x (old=0x%08x)\n", \
176 gsc_writel((value),(fb)->info.fix.mmio_start + (reg)); } while (0)
181 #define DISABLE 0
183 #define NGLE_LOCK(fb_info) do { } while (0)
184 #define NGLE_UNLOCK(fb_info) do { } while (0)
202 unsigned int reg10_value = 0; in SETUP_FB()
210 reg10_value = 0x13601000; in SETUP_FB()
214 reg10_value = 0xBBA0A000; in SETUP_FB()
216 reg10_value = 0x13601000; in SETUP_FB()
220 reg10_value = 0xBBA0A000; in SETUP_FB()
222 reg10_value = 0x13602000; in SETUP_FB()
226 reg10_value = 0x13602000; in SETUP_FB()
231 WRITE_WORD(0x83000300, fb, REG_14); in SETUP_FB()
240 WRITE_WORD(0xBBE0F000, fb, REG_10); in START_IMAGE_COLORMAP_ACCESS()
241 WRITE_WORD(0x03000300, fb, REG_14); in START_IMAGE_COLORMAP_ACCESS()
242 WRITE_WORD(~0, fb, REG_13); in START_IMAGE_COLORMAP_ACCESS()
249 WRITE_WORD(((0x100+index)<<2), fb, REG_3); in WRITE_IMAGE_COLOR()
256 WRITE_WORD(0x400, fb, REG_2); in FINISH_IMAGE_COLORMAP_ACCESS()
258 WRITE_WORD(0x83000100, fb, REG_1); in FINISH_IMAGE_COLORMAP_ACCESS()
261 WRITE_WORD(0x80000100, fb, REG_26); in FINISH_IMAGE_COLORMAP_ACCESS()
263 WRITE_WORD(0x80000100, fb, REG_1); in FINISH_IMAGE_COLORMAP_ACCESS()
272 WRITE_WORD(0x04000000, fb, 0x1020); in SETUP_RAMDAC()
273 WRITE_WORD(0xff000000, fb, 0x1028); in SETUP_RAMDAC()
280 WRITE_WORD(0x04000000, fb, 0x1000); in CRX24_SETUP_RAMDAC()
281 WRITE_WORD(0x02000000, fb, 0x1004); in CRX24_SETUP_RAMDAC()
282 WRITE_WORD(0xff000000, fb, 0x1008); in CRX24_SETUP_RAMDAC()
283 WRITE_WORD(0x05000000, fb, 0x1000); in CRX24_SETUP_RAMDAC()
284 WRITE_WORD(0x02000000, fb, 0x1004); in CRX24_SETUP_RAMDAC()
285 WRITE_WORD(0x03000000, fb, 0x1008); in CRX24_SETUP_RAMDAC()
288 #if 0
292 WRITE_WORD(0xffffffff, fb, REG_32);
300 WRITE_WORD(0x13a02000, fb, REG_11); in CRX24_SET_OVLY_MASK()
301 WRITE_WORD(0x03000300, fb, REG_14); in CRX24_SET_OVLY_MASK()
302 WRITE_WORD(0x000017f0, fb, REG_3); in CRX24_SET_OVLY_MASK()
303 WRITE_WORD(0xffffffff, fb, REG_13); in CRX24_SET_OVLY_MASK()
304 WRITE_WORD(0xffffffff, fb, REG_22); in CRX24_SET_OVLY_MASK()
305 WRITE_WORD(0x00000000, fb, REG_23); in CRX24_SET_OVLY_MASK()
311 unsigned int value = enable ? 0x43000000 : 0x03000000; in ENABLE_DISABLE_DISPLAY()
313 WRITE_WORD(0x06000000, fb, 0x1030); in ENABLE_DISABLE_DISPLAY()
314 WRITE_WORD(value, fb, 0x1038); in ENABLE_DISABLE_DISPLAY()
320 unsigned int value = enable ? 0x10000000 : 0x30000000; in CRX24_ENABLE_DISABLE_DISPLAY()
322 WRITE_WORD(0x01000000, fb, 0x1000); in CRX24_ENABLE_DISABLE_DISPLAY()
323 WRITE_WORD(0x02000000, fb, 0x1004); in CRX24_ENABLE_DISABLE_DISPLAY()
324 WRITE_WORD(value, fb, 0x1008); in CRX24_ENABLE_DISABLE_DISPLAY()
335 WRITE_WORD(READ_WORD(fb, DregsMiscVideo) | 0x0A000000, fb, DregsMiscVideo); in ARTIST_ENABLE_DISABLE_DISPLAY()
336 WRITE_WORD(READ_WORD(fb, DregsMiscCtl) | 0x00800000, fb, DregsMiscCtl); in ARTIST_ENABLE_DISABLE_DISPLAY()
338 WRITE_WORD(READ_WORD(fb, DregsMiscVideo) & ~0x0A000000, fb, DregsMiscVideo); in ARTIST_ENABLE_DISABLE_DISPLAY()
339 WRITE_WORD(READ_WORD(fb, DregsMiscCtl) & ~0x00800000, fb, DregsMiscCtl); in ARTIST_ENABLE_DISABLE_DISPLAY()
346 #define HYPER_CONFIG_PLANES_24 0x00000100
360 #define IndexedDcd 0 /* Pixel data is indexed (pseudo) color */
366 #define BINovly 0x2 /* 8 bit overlay */
367 #define BINapp0I 0x0 /* Application Buffer 0, Indexed */
368 #define BINapp1I 0x1 /* Application Buffer 1, Indexed */
369 #define BINapp0F8 0xa /* Application Buffer 0, Fractional 8-8-8 */
370 #define BINattr 0xd /* Attribute Bitmap */
371 #define RopSrc 0x3
374 #define DataDynamic 0 /* Data register reloaded by direct access */
376 #define MaskOtc 0 /* Mask contains Object Count valid bits */
437 WRITE_BYTE(0, fb, REG_16b1)
447 value |= 0x0A000000; in HYPER_ENABLE_DISABLE_DISPLAY()
449 value &= ~0x0A000000; in HYPER_ENABLE_DISABLE_DISPLAY()
455 #define BUFF0_CMAP0 0x00001e02
456 #define BUFF1_CMAP0 0x02001e02
457 #define BUFF1_CMAP3 0x0c001e02
458 #define ARTIST_CMAP0 0x00000102
459 #define HYPER_CMAP8 0x00000100
460 #define HYPER_CMAP24 0x00000800
466 WRITE_WORD(0x2EA0D000, fb, REG_11); in SETUP_ATTR_ACCESS()
467 WRITE_WORD(0x23000302, fb, REG_14); in SETUP_ATTR_ACCESS()
469 WRITE_WORD(0xffffffff, fb, REG_8); in SETUP_ATTR_ACCESS()
478 0x2f0: internal (LCD) & external display enabled in SET_ATTR_SIZE()
479 0x2a0: external display only in SET_ATTR_SIZE()
480 0x000: zero on standard artist graphic cards in SET_ATTR_SIZE()
482 WRITE_WORD(0x00000000, fb, REG_6); in SET_ATTR_SIZE()
484 WRITE_WORD(0x05000000, fb, REG_6); in SET_ATTR_SIZE()
485 WRITE_WORD(0x00040001, fb, REG_9); in SET_ATTR_SIZE()
492 WRITE_WORD(0x00000000, fb, REG_12); in FINISH_ATTR_ACCESS()
529 for (y = 0; y < fb->info.var.yres; ++y) in rattlerSetupPlanes()
531 0xff, fb->info.var.xres * fb->info.var.bits_per_pixel/8); in rattlerSetupPlanes()
538 #define HYPER_CMAP_TYPE 0
539 #define NGLE_CMAP_INDEXED0_TYPE 0
558 #if 0
565 lutBltCtl.all = 0x80000000;
573 lutBltCtl.fields.lutOffset = 0;
576 lutBltCtl.fields.lutOffset = 0 * 256;
582 lutBltCtl.fields.lutOffset = 0 * 256;
587 lutBltCtl.fields.lutOffset = 0;
604 lutBltCtl.all = 0x80000000; in setHyperLutBltCtl()
609 /* Expect lutIndex to be 0 or 1 for image cmaps, 2 or 3 for overlay cmaps */ in setHyperLutBltCtl()
613 lutBltCtl.fields.lutOffset = 0 * 256; in setHyperLutBltCtl()
624 int nFreeFifoSlots = 0; in hyperUndoITE()
630 WRITE_WORD(0xffffffff, fb, REG_32); in hyperUndoITE()
638 BAJustPoint(0), BINovly, BAIndexBase(0))); in hyperUndoITE()
640 IBOvals(RopSrc, MaskAddrOffset(0), in hyperUndoITE()
641 BitmapExtent08, StaticReg(0), in hyperUndoITE()
642 DataDynamic, MaskOtc, BGx(0), FGx(0))); in hyperUndoITE()
645 fbAddr = NGLE_LONG_FB_ADDRESS(0, 1532, 0); in hyperUndoITE()
647 NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xffffff); in hyperUndoITE()
648 NGLE_BINC_SET_DSTMASK(fb, 0xffffffff); in hyperUndoITE()
651 NGLE_BINC_WRITE32(fb, 0); in hyperUndoITE()
671 int nFreeFifoSlots = 0; in ngleResetAttrPlanes()
680 AddrLong, BAJustPoint(0), in ngleResetAttrPlanes()
681 BINattr, BAIndexBase(0))); in ngleResetAttrPlanes()
683 NGLE_SET_TRANSFERDATA(fb, 0xffffffff); in ngleResetAttrPlanes()
686 IBOvals(RopSrc, MaskAddrOffset(0), in ngleResetAttrPlanes()
689 BGx(0), FGx(0))); in ngleResetAttrPlanes()
690 packed_dst = 0; in ngleResetAttrPlanes()
715 NGLE_QUICK_SET_CTL_PLN_REG(fb, 0); in ngleResetAttrPlanes()
723 int nFreeFifoSlots = 0; in ngleClearOverlayPlanes()
733 BAJustPoint(0), BINovly, BAIndexBase(0))); in ngleClearOverlayPlanes()
735 NGLE_SET_TRANSFERDATA(fb, 0xffffffff); /* Write foreground color */ in ngleClearOverlayPlanes()
740 packed_dst = 0; in ngleClearOverlayPlanes()
746 IBOvals(RopSrc, MaskAddrOffset(0), in ngleClearOverlayPlanes()
747 BitmapExtent08, StaticReg(0), in ngleClearOverlayPlanes()
748 DataDynamic, MaskOtc, BGx(0), FGx(0))); in ngleClearOverlayPlanes()
764 controlPlaneReg = 0x04000F00; in hyperResetPlanes()
766 controlPlaneReg = 0x00000F00; /* 0x00000800 should be enough, but lets clear all 4 bits */ in hyperResetPlanes()
768 controlPlaneReg = 0x00000F00; /* 0x00000100 should be enough, but lets clear all 4 bits */ in hyperResetPlanes()
779 * On Hyperdrive, this means all windows using overlay cmap 0. */ in hyperResetPlanes()
783 ngleClearOverlayPlanes(fb, 0xff, 255); in hyperResetPlanes()
798 ngleClearOverlayPlanes(fb, 0xff, 0); in hyperResetPlanes()
815 #if 0 in ngleGetDeviceRomData()
842 while (romTableIdx > 0) in ngleGetDeviceRomData()
847 for (i = 0; i < sizePackedDevRomData; i++) in ngleGetDeviceRomData()
863 for (i = 0; i < sizePackedDevRomData; i++) in ngleGetDeviceRomData()
884 int nFreeFifoSlots = 0; in SETUP_HCRX()
903 WRITE_WORD(0x014c0148, fb, REG_42); /* Set lut 0 to be the direct color */ in SETUP_HCRX()
904 WRITE_WORD(0x404c4048, fb, REG_43); in SETUP_HCRX()
905 WRITE_WORD(0x034c0348, fb, REG_44); in SETUP_HCRX()
906 WRITE_WORD(0x444c4448, fb, REG_45); in SETUP_HCRX()
914 WRITE_WORD(0x00000000, fb, REG_42); in SETUP_HCRX()
915 WRITE_WORD(0x00000000, fb, REG_43); in SETUP_HCRX()
916 WRITE_WORD(0x00000000, fb, REG_44); in SETUP_HCRX()
917 WRITE_WORD(0x444c4048, fb, REG_45); in SETUP_HCRX()
968 0, /* Offset w/i LUT */ in stifb_setcolreg()
971 NGLE_LONG_FB_ADDRESS(0, 0x100, 0)); in stifb_setcolreg()
972 /* 0x100 is same as used in WRITE_IMAGE_COLOR() */ in stifb_setcolreg()
982 return 0; in stifb_setcolreg()
989 int enable = (blank_mode == 0) ? ENABLE : DISABLE; in stifb_blank()
1011 return 0; in stifb_blank()
1023 WRITE_WORD(0xBBA0A000, fb, REG_10); in stifb_copyarea()
1025 NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xffffffff); in stifb_copyarea()
1027 WRITE_WORD(fb->id == S9000_ID_HCRX ? 0x13a02000 : 0x13a01000, fb, REG_10); in stifb_copyarea()
1029 NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xff); in stifb_copyarea()
1033 IBOvals(RopSrc, MaskAddrOffset(0), in stifb_copyarea()
1035 DataDynamic, MaskOtc, BGx(0), FGx(0))); in stifb_copyarea()
1086 ngleClearOverlayPlanes(fb, 0xff, 0); in stifb_init_display()
1097 stifb_blank(0, (struct fb_info *)fb); /* 0=enable screen */ in stifb_init_display()
1141 fb->id = fb->sti->graphics_id[0]; in stifb_init_fb()
1168 printk(KERN_WARNING "stifb: '%s' (id: 0x%08x) not supported.\n", in stifb_init_fb()
1182 fix->mmio_len = 0x400000; in stifb_init_fb()
1211 memset(&fb->ngle_rom, 0, sizeof(fb->ngle_rom)); in stifb_init_fb()
1212 if ((fb->sti->regions_phys[0] & 0xfc000000) == in stifb_init_fb()
1213 (fb->sti->regions_phys[2] & 0xfc000000)) in stifb_init_fb()
1214 sti_rom_address = F_EXTEND(fb->sti->regions_phys[0]); in stifb_init_fb()
1235 "stifb: Unsupported graphics card (id=0x%08x) " in stifb_init_fb()
1242 "stifb: Unsupported graphics card (id=0x%08x) " in stifb_init_fb()
1279 var->blue.offset = 0; in stifb_init_fb()
1304 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0)) in stifb_init_fb()
1309 printk(KERN_ERR "stifb: cannot reserve fb region 0x%04lx-0x%04lx\n", in stifb_init_fb()
1315 printk(KERN_ERR "stifb: cannot reserve sti mmio region 0x%04lx-0x%04lx\n", in stifb_init_fb()
1320 if (register_framebuffer(&fb->info) < 0) in stifb_init_fb()
1325 fb_info(&fb->info, "%s %dx%d-%d frame buffer device, %s, id: %04x, mmio: 0x%04lx\n", in stifb_init_fb()
1334 return 0; in stifb_init_fb()
1373 def_sti = sti_get_rom(0); in stifb_init()
1394 return 0; in stifb_init()
1433 if (strncmp(options, "off", 3) == 0) { in stifb_setup()
1438 if (strncmp(options, "bpp", 3) == 0) { in stifb_setup()
1440 for (i = 0; i < MAX_STI_ROMS; i++) { in stifb_setup()