Lines Matching +full:0 +full:x67
50 { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
52 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 0,
53 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
54 { 4, {0, 4, 0}, {0, 4, 0}, {0, 4, 0}, {0, 0, 0}, 1,
56 { 8, {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
57 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
58 {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
59 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
60 {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
61 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
62 {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
63 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
64 {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
65 FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
70 static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
72 static const struct svga_pll s3_trio3d_pll = {3, 129, 3, 31, 0, 4,
75 static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
85 #define CHIP_UNKNOWN 0x00
86 #define CHIP_732_TRIO32 0x01
87 #define CHIP_764_TRIO64 0x02
88 #define CHIP_765_TRIO64VP 0x03
89 #define CHIP_767_TRIO64UVP 0x04
90 #define CHIP_775_TRIO64V2_DX 0x05
91 #define CHIP_785_TRIO64V2_GX 0x06
92 #define CHIP_551_PLATO_PX 0x07
93 #define CHIP_M65_AURORA64VP 0x08
94 #define CHIP_325_VIRGE 0x09
95 #define CHIP_988_VIRGE_VX 0x0A
96 #define CHIP_375_VIRGE_DX 0x0B
97 #define CHIP_385_VIRGE_GX 0x0C
98 #define CHIP_357_VIRGE_GX2 0x0D
99 #define CHIP_359_VIRGE_GX2P 0x0E
100 #define CHIP_360_TRIO3D_1X 0x10
101 #define CHIP_362_TRIO3D_2X 0x11
102 #define CHIP_368_TRIO3D_2X 0x12
103 #define CHIP_365_TRIO3D 0x13
104 #define CHIP_260_VIRGE_MX 0x14
106 #define CHIP_XXX_TRIO 0x80
107 #define CHIP_XXX_TRIO64V2_DXGX 0x81
108 #define CHIP_XXX_VIRGE_DXGX 0x82
109 #define CHIP_36X_TRIO3D_1X_2X 0x83
111 #define CHIP_UNDECIDED_FLAG 0x80
112 #define CHIP_MASK 0xFF
114 #define MMIO_OFFSET 0x1000000
115 #define MMIO_SIZE 0x10000
119 static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_E…
120 static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_E…
121 static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_E…
122 static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_E…
123 static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_E…
124 static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
126 …st struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, …
127 …c const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0…
128 …c const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0…
129 static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
130 …c const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0…
131 static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
133 …c const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0…
134 static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x69, 0, 4}…
135 …ct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43…
137 static const struct vga_regset s3_dtpc_regs[] = {{0x3B, 0, 7}, {0x5D, 6, 6}, VGA_REGSET_END};
166 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
169 MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
176 #define DDC_REG 0xaa /* Trio 3D/1X/2X */
177 #define DDC_MMIO_REG 0xff20 /* all other chips */
178 #define DDC_SCL_OUT (1 << 0)
271 /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */ in s3fb_setup_ddc_bus()
275 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); in s3fb_setup_ddc_bus()
277 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); in s3fb_setup_ddc_bus()
279 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03); in s3fb_setup_ddc_bus()
304 for (i = 0; i < map->height; i++) { in s3fb_settile_fast()
305 for (c = 0; c < map->length; c++) { in s3fb_settile_fast()
343 return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; in expand_color()
361 for (y = 0; y < image->height; y++) { in s3fb_iplan_imageblit()
364 for (x = 0; x < image->width; x += 8) { in s3fb_iplan_imageblit()
365 val = *(src++) * 0x01010101; in s3fb_iplan_imageblit()
386 for (y = 0; y < rect->height; y++) { in s3fb_iplan_fillrect()
388 for (x = 0; x < rect->width; x += 8) { in s3fb_iplan_fillrect()
400 ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; in expand_pixel()
406 u32 fg = image->fg_color * 0x11111111; in s3fb_cfb4_imageblit()
407 u32 bg = image->bg_color * 0x11111111; in s3fb_cfb4_imageblit()
418 for (y = 0; y < image->height; y++) { in s3fb_cfb4_imageblit()
421 for (x = 0; x < image->width; x += 8) { in s3fb_cfb4_imageblit()
434 && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { in s3fb_imageblit()
446 && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) in s3fb_fillrect()
467 if (rv < 0) { in s3_set_pixclock()
483 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ in s3_set_pixclock()
484 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ in s3_set_pixclock()
486 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); in s3_set_pixclock()
487 vga_wseq(par->state.vgabase, 0x13, m - 2); in s3_set_pixclock()
491 /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */ in s3_set_pixclock()
492 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ in s3_set_pixclock()
493 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
494 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); in s3_set_pixclock()
495 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
506 if (par->ref_count == 0) { in s3fb_open()
509 memset(&(par->state), 0, sizeof(struct vgastate)); in s3fb_open()
512 par->state.num_crtc = 0x70; in s3fb_open()
513 par->state.num_seq = 0x20; in s3fb_open()
520 return 0; in s3fb_open()
530 if (par->ref_count == 0) { in s3fb_release()
541 return 0; in s3fb_release()
560 if (rv < 0) { in s3fb_check_var()
585 if (rv < 0) { in s3fb_check_var()
592 if (rv < 0) { in s3fb_check_var()
597 return 0; in s3fb_check_var()
609 if (bpp != 0) { in s3fb_set_par()
617 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); in s3fb_set_par()
618 info->pixmap.blit_y = ~(u32)0; in s3fb_set_par()
624 info->fix.line_length = 0; in s3fb_set_par()
637 info->var.xoffset = 0; in s3fb_set_par()
638 info->var.yoffset = 0; in s3fb_set_par()
642 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3fb_set_par()
643 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3fb_set_par()
644 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3fb_set_par()
645 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); in s3fb_set_par()
648 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_set_par()
649 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); in s3fb_set_par()
656 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); in s3fb_set_par()
657 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); in s3fb_set_par()
660 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ in s3fb_set_par()
661 …svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer ab… in s3fb_set_par()
663 /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */ in s3fb_set_par()
664 /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */ in s3fb_set_par()
665 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ in s3fb_set_par()
666 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ in s3fb_set_par()
668 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ in s3fb_set_par()
670 /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */ in s3fb_set_par()
672 /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */ in s3fb_set_par()
673 /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */ in s3fb_set_par()
686 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ in s3fb_set_par()
687 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ in s3fb_set_par()
688 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ in s3fb_set_par()
689 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ in s3fb_set_par()
692 vga_wcrt(par->state.vgabase, 0x3A, 0x35); in s3fb_set_par()
693 svga_wattr(par->state.vgabase, 0x33, 0x00); in s3fb_set_par()
696 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); in s3fb_set_par()
698 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); in s3fb_set_par()
701 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); in s3fb_set_par()
703 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); in s3fb_set_par()
706 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); in s3fb_set_par()
708 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); in s3fb_set_par()
714 vga_wcrt(par->state.vgabase, 0x86, 0x80); in s3fb_set_par()
715 vga_wcrt(par->state.vgabase, 0x90, 0x00); in s3fb_set_par()
720 vga_wcrt(par->state.vgabase, 0x50, 0x00); in s3fb_set_par()
721 vga_wcrt(par->state.vgabase, 0x67, 0x50); in s3fb_set_par()
723 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); in s3fb_set_par()
724 vga_wcrt(par->state.vgabase, 0x66, 0x90); in s3fb_set_par()
737 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); in s3fb_set_par()
738 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); in s3fb_set_par()
740 vga_wcrt(par->state.vgabase, 0x66, 0x81); in s3fb_set_par()
749 vga_wcrt(par->state.vgabase, 0x34, 0x00); in s3fb_set_par()
751 vga_wcrt(par->state.vgabase, 0x34, 0x10); in s3fb_set_par()
753 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); in s3fb_set_par()
754 multiplex = 0; in s3fb_set_par()
759 case 0: in s3fb_set_par()
764 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
765 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
768 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
772 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); in s3fb_set_par()
777 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); in s3fb_set_par()
780 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
781 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
784 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
790 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
791 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
794 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
798 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
806 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
808 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); in s3fb_set_par()
816 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
818 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
820 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
822 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
825 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
829 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
830 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
844 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
846 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
848 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
850 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
853 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
857 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
858 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
871 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
875 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); in s3fb_set_par()
876 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
884 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); in s3fb_set_par()
885 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); in s3fb_set_par()
897 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2); in s3fb_set_par()
905 memset_io(info->screen_base, 0x00, screen_size); in s3fb_set_par()
907 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); in s3fb_set_par()
908 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_set_par()
910 return 0; in s3fb_set_par()
919 case 0: in s3fb_setcolreg()
925 (fb->var.nonstd == 0)) { in s3fb_setcolreg()
926 outb(0xF0, VGA_PEL_MSK); in s3fb_setcolreg()
929 outb(0x0F, VGA_PEL_MSK); in s3fb_setcolreg()
940 outb(0xFF, VGA_PEL_MSK); in s3fb_setcolreg()
948 return 0; in s3fb_setcolreg()
951 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | in s3fb_setcolreg()
952 ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); in s3fb_setcolreg()
954 ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | in s3fb_setcolreg()
955 ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); in s3fb_setcolreg()
961 return 0; in s3fb_setcolreg()
963 ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | in s3fb_setcolreg()
964 (green & 0xFF00) | ((blue & 0xFF00) >> 8); in s3fb_setcolreg()
970 return 0; in s3fb_setcolreg()
983 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
984 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_blank()
988 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
989 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
993 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); in s3fb_blank()
994 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
998 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); in s3fb_blank()
999 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1003 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); in s3fb_blank()
1004 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1008 return 0; in s3fb_blank()
1020 if (info->var.bits_per_pixel == 0) { in s3fb_pan_display()
1033 return 0; in s3fb_pan_display()
1062 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); in s3_identification()
1063 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); in s3_identification()
1064 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); in s3_identification()
1066 if ((cr30 == 0xE0) || (cr30 == 0xE1)) { in s3_identification()
1067 if (cr2e == 0x10) in s3_identification()
1069 if (cr2e == 0x11) { in s3_identification()
1070 if (! (cr2f & 0x40)) in s3_identification()
1079 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1081 if (! (cr6f & 0x01)) in s3_identification()
1088 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1090 if (! (cr6f & 0x01)) in s3_identification()
1097 switch (vga_rcrt(par->state.vgabase, 0x2f)) { in s3_identification()
1098 case 0x00: in s3_identification()
1100 case 0x01: in s3_identification()
1102 case 0x02: in s3_identification()
1142 if (rc < 0) { in s3_pci_probe()
1148 if (rc < 0) { in s3_pci_probe()
1154 info->fix.smem_start = pci_resource_start(dev, 0); in s3_pci_probe()
1155 info->fix.smem_len = pci_resource_len(dev, 0); in s3_pci_probe()
1158 info->screen_base = pci_iomap_wc(dev, 0, 0); in s3_pci_probe()
1165 bus_reg.start = 0; in s3_pci_probe()
1175 cr38 = vga_rcrt(par->state.vgabase, 0x38); in s3_pci_probe()
1176 cr39 = vga_rcrt(par->state.vgabase, 0x39); in s3_pci_probe()
1177 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3_pci_probe()
1178 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3_pci_probe()
1179 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3_pci_probe()
1183 par->rev = vga_rcrt(par->state.vgabase, 0x2f); in s3_pci_probe()
1188 /* 0x36 register is accessible even if other registers are locked */ in s3_pci_probe()
1189 regval = vga_rcrt(par->state.vgabase, 0x36); in s3_pci_probe()
1194 switch ((regval & 0xE0) >> 5) { in s3_pci_probe()
1195 case 0: /* 8MB -- only 4MB usable for display */ in s3_pci_probe()
1208 switch ((regval & 0xC0) >> 6) { in s3_pci_probe()
1217 switch ((regval & 0x60) >> 5) { in s3_pci_probe()
1218 case 0: /* 2MB */ in s3_pci_probe()
1232 regval = vga_rcrt(par->state.vgabase, 0x37); in s3_pci_probe()
1233 switch ((regval & 0x60) >> 5) { in s3_pci_probe()
1246 regval = vga_rseq(par->state.vgabase, 0x10); in s3_pci_probe()
1247 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); in s3_pci_probe()
1251 vga_wcrt(par->state.vgabase, 0x38, cr38); in s3_pci_probe()
1252 vga_wcrt(par->state.vgabase, 0x39, cr39); in s3_pci_probe()
1255 info->fix.mmio_start = 0; in s3_pci_probe()
1256 info->fix.mmio_len = 0; in s3_pci_probe()
1259 info->fix.ypanstep = 0; in s3_pci_probe()
1269 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */ in s3_pci_probe()
1271 dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC", in s3_pci_probe()
1275 if (s3fb_setup_ddc_bus(info) == 0) { in s3_pci_probe()
1293 if (s3fb_check_var(&info->var, info) == 0) in s3_pci_probe()
1329 rc = fb_alloc_cmap(&info->cmap, 256, 0); in s3_pci_probe()
1330 if (rc < 0) { in s3_pci_probe()
1336 if (rc < 0) { in s3_pci_probe()
1347 vga_rcrt(par->state.vgabase, 0x2d), in s3_pci_probe()
1348 vga_rcrt(par->state.vgabase, 0x2e), in s3_pci_probe()
1349 vga_rcrt(par->state.vgabase, 0x2f), in s3_pci_probe()
1350 vga_rcrt(par->state.vgabase, 0x30)); in s3_pci_probe()
1359 return 0; in s3_pci_probe()
1423 if (par->ref_count == 0) { in s3_pci_suspend()
1426 return 0; in s3_pci_suspend()
1434 return 0; in s3_pci_suspend()
1450 if (par->ref_count == 0) { in s3_pci_resume()
1453 return 0; in s3_pci_resume()
1457 fb_set_suspend(info, 0); in s3_pci_resume()
1462 return 0; in s3_pci_resume()
1479 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
1480 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
1481 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
1482 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
1483 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
1484 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
1486 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
1487 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
1488 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
1489 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_357_VIRGE_GX2},
1490 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_359_VIRGE_GX2P},
1491 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
1492 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
1493 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D},
1494 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8C01), .driver_data = CHIP_260_VIRGE_MX},
1496 {0, 0, 0, 0, 0, 0, 0}
1518 return 0; in s3fb_setup()
1525 mtrr = simple_strtoul(opt + 5, NULL, 0); in s3fb_setup()
1527 fasttext = simple_strtoul(opt + 9, NULL, 0); in s3fb_setup()
1532 return 0; in s3fb_setup()