Lines Matching refs:mclks
660 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; in nv4CalcArbitration() local
686 mclks = 5; in nv4CalcArbitration()
687 mclks += 3; in nv4CalcArbitration()
688 mclks += 1; in nv4CalcArbitration()
689 mclks += cas; in nv4CalcArbitration()
690 mclks += 1; in nv4CalcArbitration()
691 mclks += 1; in nv4CalcArbitration()
692 mclks += 1; in nv4CalcArbitration()
693 mclks += 1; in nv4CalcArbitration()
700 mclks+=4; in nv4CalcArbitration()
709 mclk_loop = mclks+mclk_extra; in nv4CalcArbitration()
846 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; in nv10CalcArbitration() local
881 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */ in nv10CalcArbitration()
883 mclks += 1; /* arb_hp_req */ in nv10CalcArbitration()
884 mclks += 5; /* ap_hp_req tiling pipeline */ in nv10CalcArbitration()
886 mclks += 2; /* tc_req latency fifo */ in nv10CalcArbitration()
887 mclks += 2; /* fb_cas_n_ memory request to fbio block */ in nv10CalcArbitration()
888 mclks += 7; /* sm_d_rdv data returned from fbio block */ in nv10CalcArbitration()
893 mclks += 4; in nv10CalcArbitration()
895 mclks += 2; in nv10CalcArbitration()
898 mclks += 2; in nv10CalcArbitration()
900 mclks += 1; in nv10CalcArbitration()
920 mclks+=4; /* Mp can get in with a burst of 8. */ in nv10CalcArbitration()
929 mclk_loop = mclks+mclk_extra; in nv10CalcArbitration()
931 us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */ in nv10CalcArbitration()