Lines Matching +full:offset +full:- +full:x
2 * linux/drivers/video/pxa168fb.c -- Marvell PXA168 LCD Controller
7 * 2009-02-16 adapted from original version for PXA168/910
27 #include <linux/dma-mapping.h>
42 if (var->bits_per_pixel == 8) in determine_best_pix_fmt()
48 if (var->bits_per_pixel == 16 && var->red.length <= 5 && in determine_best_pix_fmt()
49 var->green.length <= 6 && var->blue.length <= 5) { in determine_best_pix_fmt()
50 if (var->transp.length == 0) { in determine_best_pix_fmt()
51 if (var->red.offset >= var->blue.offset) in determine_best_pix_fmt()
57 if (var->transp.length == 1 && var->green.length <= 5) { in determine_best_pix_fmt()
58 if (var->red.offset >= var->blue.offset) in determine_best_pix_fmt()
68 if (var->bits_per_pixel <= 32 && var->red.length <= 8 && in determine_best_pix_fmt()
69 var->green.length <= 8 && var->blue.length <= 8) { in determine_best_pix_fmt()
70 if (var->bits_per_pixel == 24 && var->transp.length == 0) { in determine_best_pix_fmt()
71 if (var->red.offset >= var->blue.offset) in determine_best_pix_fmt()
77 if (var->bits_per_pixel == 32 && var->transp.length == 8) { in determine_best_pix_fmt()
78 if (var->red.offset >= var->blue.offset) in determine_best_pix_fmt()
83 if (var->red.offset >= var->blue.offset) in determine_best_pix_fmt()
90 return -EINVAL; in determine_best_pix_fmt()
97 var->bits_per_pixel = 16; in set_pix_fmt()
98 var->red.offset = 11; var->red.length = 5; in set_pix_fmt()
99 var->green.offset = 5; var->green.length = 6; in set_pix_fmt()
100 var->blue.offset = 0; var->blue.length = 5; in set_pix_fmt()
101 var->transp.offset = 0; var->transp.length = 0; in set_pix_fmt()
104 var->bits_per_pixel = 16; in set_pix_fmt()
105 var->red.offset = 0; var->red.length = 5; in set_pix_fmt()
106 var->green.offset = 5; var->green.length = 6; in set_pix_fmt()
107 var->blue.offset = 11; var->blue.length = 5; in set_pix_fmt()
108 var->transp.offset = 0; var->transp.length = 0; in set_pix_fmt()
111 var->bits_per_pixel = 16; in set_pix_fmt()
112 var->red.offset = 10; var->red.length = 5; in set_pix_fmt()
113 var->green.offset = 5; var->green.length = 5; in set_pix_fmt()
114 var->blue.offset = 0; var->blue.length = 5; in set_pix_fmt()
115 var->transp.offset = 15; var->transp.length = 1; in set_pix_fmt()
118 var->bits_per_pixel = 16; in set_pix_fmt()
119 var->red.offset = 0; var->red.length = 5; in set_pix_fmt()
120 var->green.offset = 5; var->green.length = 5; in set_pix_fmt()
121 var->blue.offset = 10; var->blue.length = 5; in set_pix_fmt()
122 var->transp.offset = 15; var->transp.length = 1; in set_pix_fmt()
125 var->bits_per_pixel = 24; in set_pix_fmt()
126 var->red.offset = 16; var->red.length = 8; in set_pix_fmt()
127 var->green.offset = 8; var->green.length = 8; in set_pix_fmt()
128 var->blue.offset = 0; var->blue.length = 8; in set_pix_fmt()
129 var->transp.offset = 0; var->transp.length = 0; in set_pix_fmt()
132 var->bits_per_pixel = 24; in set_pix_fmt()
133 var->red.offset = 0; var->red.length = 8; in set_pix_fmt()
134 var->green.offset = 8; var->green.length = 8; in set_pix_fmt()
135 var->blue.offset = 16; var->blue.length = 8; in set_pix_fmt()
136 var->transp.offset = 0; var->transp.length = 0; in set_pix_fmt()
139 var->bits_per_pixel = 32; in set_pix_fmt()
140 var->red.offset = 16; var->red.length = 8; in set_pix_fmt()
141 var->green.offset = 8; var->green.length = 8; in set_pix_fmt()
142 var->blue.offset = 0; var->blue.length = 8; in set_pix_fmt()
143 var->transp.offset = 24; var->transp.length = 8; in set_pix_fmt()
146 var->bits_per_pixel = 32; in set_pix_fmt()
147 var->red.offset = 0; var->red.length = 8; in set_pix_fmt()
148 var->green.offset = 8; var->green.length = 8; in set_pix_fmt()
149 var->blue.offset = 16; var->blue.length = 8; in set_pix_fmt()
150 var->transp.offset = 24; var->transp.length = 8; in set_pix_fmt()
153 var->bits_per_pixel = 8; in set_pix_fmt()
154 var->red.offset = 0; var->red.length = 8; in set_pix_fmt()
155 var->green.offset = 0; var->green.length = 8; in set_pix_fmt()
156 var->blue.offset = 0; var->blue.length = 8; in set_pix_fmt()
157 var->transp.offset = 0; var->transp.length = 0; in set_pix_fmt()
165 struct fb_info *info = fbi->info; in set_mode()
169 var->xres = mode->xres; in set_mode()
170 var->yres = mode->yres; in set_mode()
171 var->xres_virtual = max(var->xres, var->xres_virtual); in set_mode()
173 var->yres_virtual = info->fix.smem_len / in set_mode()
174 (var->xres_virtual * (var->bits_per_pixel >> 3)); in set_mode()
176 var->yres_virtual = max(var->yres, var->yres_virtual); in set_mode()
177 var->grayscale = 0; in set_mode()
178 var->accel_flags = FB_ACCEL_NONE; in set_mode()
179 var->pixclock = mode->pixclock; in set_mode()
180 var->left_margin = mode->left_margin; in set_mode()
181 var->right_margin = mode->right_margin; in set_mode()
182 var->upper_margin = mode->upper_margin; in set_mode()
183 var->lower_margin = mode->lower_margin; in set_mode()
184 var->hsync_len = mode->hsync_len; in set_mode()
185 var->vsync_len = mode->vsync_len; in set_mode()
186 var->sync = mode->sync; in set_mode()
187 var->vmode = FB_VMODE_NONINTERLACED; in set_mode()
188 var->rotate = FB_ROTATE_UR; in set_mode()
194 struct pxa168fb_info *fbi = info->par; in pxa168fb_check_var()
204 fbi->pix_fmt = pix_fmt; in pxa168fb_check_var()
209 if (var->xoffset + var->xres > var->xres_virtual) in pxa168fb_check_var()
210 return -EINVAL; in pxa168fb_check_var()
211 if (var->yoffset + var->yres > var->yres_virtual) in pxa168fb_check_var()
212 return -EINVAL; in pxa168fb_check_var()
213 if (var->xres + var->right_margin + in pxa168fb_check_var()
214 var->hsync_len + var->left_margin > 2048) in pxa168fb_check_var()
215 return -EINVAL; in pxa168fb_check_var()
216 if (var->yres + var->lower_margin + in pxa168fb_check_var()
217 var->vsync_len + var->upper_margin > 2048) in pxa168fb_check_var()
218 return -EINVAL; in pxa168fb_check_var()
223 if (var->xres_virtual * var->yres_virtual * in pxa168fb_check_var()
224 (var->bits_per_pixel >> 3) > info->fix.smem_len) in pxa168fb_check_var()
225 return -EINVAL; in pxa168fb_check_var()
235 * clk_out = clk2 * (1 - (fractional_divider >> 12))
246 u32 x = 0; in set_clock_divider() local
257 if (!m || !m->pixclock || !m->refresh) { in set_clock_divider()
258 dev_err(fbi->dev, "Input refresh or pixclock is wrong.\n"); in set_clock_divider()
265 x = 0x80000000; in set_clock_divider()
271 do_div(div_result, m->pixclock); in set_clock_divider()
274 divider_int = clk_get_rate(fbi->clk) / needed_pixclk; in set_clock_divider()
278 dev_warn(fbi->dev, "Warning: clock source is too slow. " in set_clock_divider()
286 x |= divider_int; in set_clock_divider()
287 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); in set_clock_divider()
292 u32 x; in set_dma_control0() local
297 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0()
298 x &= ~CFG_GRA_ENA_MASK; in set_dma_control0()
299 x |= fbi->active ? CFG_GRA_ENA(1) : CFG_GRA_ENA(0); in set_dma_control0()
302 * If we are in a pseudo-color mode, we need to enable in set_dma_control0()
305 if (fbi->pix_fmt == PIX_FMT_PSEUDOCOLOR) in set_dma_control0()
306 x |= 0x10000000; in set_dma_control0()
311 x &= ~(0xF << 16); in set_dma_control0()
312 x |= (fbi->pix_fmt >> 1) << 16; in set_dma_control0()
319 x &= ~(1 << 12); in set_dma_control0()
320 x |= ((fbi->pix_fmt & 1) ^ (fbi->panel_rbswap)) << 12; in set_dma_control0()
322 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0()
327 u32 x; in set_dma_control1() local
334 x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL1); in set_dma_control1()
335 x |= 0x2032ff81; in set_dma_control1()
342 x |= 0x08000000; in set_dma_control1()
344 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1); in set_dma_control1()
349 struct pxa168fb_info *fbi = info->par; in set_graphics_start()
350 struct fb_var_screeninfo *var = &info->var; in set_graphics_start()
354 pixel_offset = (yoffset * var->xres_virtual) + xoffset; in set_graphics_start()
356 addr = fbi->fb_start_dma + (pixel_offset * (var->bits_per_pixel >> 3)); in set_graphics_start()
357 writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0); in set_graphics_start()
362 struct pxa168fb_info *fbi = info->par; in set_dumb_panel_control()
363 struct pxa168fb_mach_info *mi = dev_get_platdata(fbi->dev); in set_dumb_panel_control()
364 u32 x; in set_dumb_panel_control() local
369 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL) & 0x00000001; in set_dumb_panel_control()
371 x |= (fbi->is_blanked ? 0x7 : mi->dumb_mode) << 28; in set_dumb_panel_control()
372 x |= mi->gpio_output_data << 20; in set_dumb_panel_control()
373 x |= mi->gpio_output_mask << 12; in set_dumb_panel_control()
374 x |= mi->panel_rgb_reverse_lanes ? 0x00000080 : 0; in set_dumb_panel_control()
375 x |= mi->invert_composite_blank ? 0x00000040 : 0; in set_dumb_panel_control()
376 x |= (info->var.sync & FB_SYNC_COMP_HIGH_ACT) ? 0x00000020 : 0; in set_dumb_panel_control()
377 x |= mi->invert_pix_val_ena ? 0x00000010 : 0; in set_dumb_panel_control()
378 x |= (info->var.sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x00000008; in set_dumb_panel_control()
379 x |= (info->var.sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x00000004; in set_dumb_panel_control()
380 x |= mi->invert_pixclock ? 0x00000002 : 0; in set_dumb_panel_control()
382 writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL); in set_dumb_panel_control()
387 struct pxa168fb_info *fbi = info->par; in set_dumb_screen_dimensions()
388 struct fb_var_screeninfo *v = &info->var; in set_dumb_screen_dimensions()
389 int x; in set_dumb_screen_dimensions() local
392 x = v->xres + v->right_margin + v->hsync_len + v->left_margin; in set_dumb_screen_dimensions()
393 y = v->yres + v->lower_margin + v->vsync_len + v->upper_margin; in set_dumb_screen_dimensions()
395 writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL); in set_dumb_screen_dimensions()
400 struct pxa168fb_info *fbi = info->par; in pxa168fb_set_par()
401 struct fb_var_screeninfo *var = &info->var; in pxa168fb_set_par()
403 u32 x; in pxa168fb_set_par() local
408 if (fbi->pix_fmt == PIX_FMT_PSEUDOCOLOR) in pxa168fb_set_par()
409 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; in pxa168fb_set_par()
411 info->fix.visual = FB_VISUAL_TRUECOLOR; in pxa168fb_set_par()
412 info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8; in pxa168fb_set_par()
413 info->fix.ypanstep = var->yres; in pxa168fb_set_par()
418 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL); in pxa168fb_set_par()
419 writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL); in pxa168fb_set_par()
424 writel((var->yres << 16) | var->xres, in pxa168fb_set_par()
425 fbi->reg_base + LCD_SPU_V_H_ACTIVE); in pxa168fb_set_par()
430 fb_var_to_videomode(&mode, &info->var); in pxa168fb_set_par()
437 set_dma_control1(fbi, info->var.sync); in pxa168fb_set_par()
442 x = readl(fbi->reg_base + LCD_CFG_GRA_PITCH); in pxa168fb_set_par()
443 x = (x & ~0xFFFF) | ((var->xres_virtual * var->bits_per_pixel) >> 3); in pxa168fb_set_par()
444 writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH); in pxa168fb_set_par()
445 writel((var->yres << 16) | var->xres, in pxa168fb_set_par()
446 fbi->reg_base + LCD_SPU_GRA_HPXL_VLN); in pxa168fb_set_par()
447 writel((var->yres << 16) | var->xres, in pxa168fb_set_par()
448 fbi->reg_base + LCD_SPU_GZM_HPXL_VLN); in pxa168fb_set_par()
456 writel((var->left_margin << 16) | var->right_margin, in pxa168fb_set_par()
457 fbi->reg_base + LCD_SPU_H_PORCH); in pxa168fb_set_par()
458 writel((var->upper_margin << 16) | var->lower_margin, in pxa168fb_set_par()
459 fbi->reg_base + LCD_SPU_V_PORCH); in pxa168fb_set_par()
462 * Re-enable panel output. in pxa168fb_set_par()
464 x = readl(fbi->reg_base + LCD_SPU_DUMB_CTRL); in pxa168fb_set_par()
465 writel(x | 1, fbi->reg_base + LCD_SPU_DUMB_CTRL); in pxa168fb_set_par()
472 return ((chan & 0xffff) >> (16 - bf->length)) << bf->offset; in chan_to_field()
488 struct pxa168fb_info *fbi = info->par; in pxa168fb_setcolreg()
491 if (info->var.grayscale) in pxa168fb_setcolreg()
495 if (info->fix.visual == FB_VISUAL_TRUECOLOR && regno < 16) { in pxa168fb_setcolreg()
496 val = chan_to_field(red, &info->var.red); in pxa168fb_setcolreg()
497 val |= chan_to_field(green, &info->var.green); in pxa168fb_setcolreg()
498 val |= chan_to_field(blue , &info->var.blue); in pxa168fb_setcolreg()
499 fbi->pseudo_palette[regno] = val; in pxa168fb_setcolreg()
502 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) { in pxa168fb_setcolreg()
504 writel(val, fbi->reg_base + LCD_SPU_SRAM_WRDAT); in pxa168fb_setcolreg()
505 writel(0x8300 | regno, fbi->reg_base + LCD_SPU_SRAM_CTRL); in pxa168fb_setcolreg()
513 struct pxa168fb_info *fbi = info->par; in pxa168fb_blank()
515 fbi->is_blanked = (blank == FB_BLANK_UNBLANK) ? 0 : 1; in pxa168fb_blank()
524 set_graphics_start(info, var->xoffset, var->yoffset); in pxa168fb_pan_display()
532 u32 isr = readl(fbi->reg_base + SPU_IRQ_ISR); in pxa168fb_handle_irq()
537 fbi->reg_base + SPU_IRQ_ISR); in pxa168fb_handle_irq()
559 struct pxa168fb_info *fbi = info->par; in pxa168fb_init_mode()
560 struct fb_var_screeninfo *var = &info->var; in pxa168fb_init_mode()
571 m = fb_find_best_mode(&info->var, &info->modelist); in pxa168fb_init_mode()
573 fb_videomode_to_var(&info->var, m); in pxa168fb_init_mode()
576 var->xres_virtual = var->xres; in pxa168fb_init_mode()
577 var->yres_virtual = info->fix.smem_len / in pxa168fb_init_mode()
578 (var->xres_virtual * (var->bits_per_pixel >> 3)); in pxa168fb_init_mode()
579 dev_dbg(fbi->dev, "pxa168fb: find best mode: res = %dx%d\n", in pxa168fb_init_mode()
580 var->xres, var->yres); in pxa168fb_init_mode()
583 total_w = var->xres + var->left_margin + var->right_margin + in pxa168fb_init_mode()
584 var->hsync_len; in pxa168fb_init_mode()
585 total_h = var->yres + var->upper_margin + var->lower_margin + in pxa168fb_init_mode()
586 var->vsync_len; in pxa168fb_init_mode()
590 var->pixclock = (u32)div_result; in pxa168fb_init_mode()
602 mi = dev_get_platdata(&pdev->dev); in pxa168fb_probe()
604 dev_err(&pdev->dev, "no platform data defined\n"); in pxa168fb_probe()
605 return -EINVAL; in pxa168fb_probe()
608 clk = devm_clk_get(&pdev->dev, "LCDCLK"); in pxa168fb_probe()
610 dev_err(&pdev->dev, "unable to get LCDCLK"); in pxa168fb_probe()
616 dev_err(&pdev->dev, "no IO memory defined\n"); in pxa168fb_probe()
617 return -ENOENT; in pxa168fb_probe()
622 dev_err(&pdev->dev, "no IRQ defined\n"); in pxa168fb_probe()
623 return -ENOENT; in pxa168fb_probe()
626 info = framebuffer_alloc(sizeof(struct pxa168fb_info), &pdev->dev); in pxa168fb_probe()
628 return -ENOMEM; in pxa168fb_probe()
632 fbi = info->par; in pxa168fb_probe()
633 fbi->info = info; in pxa168fb_probe()
634 fbi->clk = clk; in pxa168fb_probe()
635 fbi->dev = info->dev = &pdev->dev; in pxa168fb_probe()
636 fbi->panel_rbswap = mi->panel_rbswap; in pxa168fb_probe()
637 fbi->is_blanked = 0; in pxa168fb_probe()
638 fbi->active = mi->active; in pxa168fb_probe()
643 info->flags = FBINFO_DEFAULT | FBINFO_PARTIAL_PAN_OK | in pxa168fb_probe()
645 info->node = -1; in pxa168fb_probe()
646 strlcpy(info->fix.id, mi->id, 16); in pxa168fb_probe()
647 info->fix.type = FB_TYPE_PACKED_PIXELS; in pxa168fb_probe()
648 info->fix.type_aux = 0; in pxa168fb_probe()
649 info->fix.xpanstep = 0; in pxa168fb_probe()
650 info->fix.ypanstep = 0; in pxa168fb_probe()
651 info->fix.ywrapstep = 0; in pxa168fb_probe()
652 info->fix.mmio_start = res->start; in pxa168fb_probe()
653 info->fix.mmio_len = resource_size(res); in pxa168fb_probe()
654 info->fix.accel = FB_ACCEL_NONE; in pxa168fb_probe()
655 info->fbops = &pxa168fb_ops; in pxa168fb_probe()
656 info->pseudo_palette = fbi->pseudo_palette; in pxa168fb_probe()
661 fbi->reg_base = devm_ioremap(&pdev->dev, res->start, in pxa168fb_probe()
663 if (fbi->reg_base == NULL) { in pxa168fb_probe()
664 ret = -ENOMEM; in pxa168fb_probe()
671 info->fix.smem_len = PAGE_ALIGN(DEFAULT_FB_SIZE); in pxa168fb_probe()
673 info->screen_base = dma_alloc_wc(fbi->dev, info->fix.smem_len, in pxa168fb_probe()
674 &fbi->fb_start_dma, GFP_KERNEL); in pxa168fb_probe()
675 if (info->screen_base == NULL) { in pxa168fb_probe()
676 ret = -ENOMEM; in pxa168fb_probe()
680 info->fix.smem_start = (unsigned long)fbi->fb_start_dma; in pxa168fb_probe()
686 set_mode(fbi, &info->var, mi->modes, mi->pix_fmt, 1); in pxa168fb_probe()
688 fb_videomode_to_modelist(mi->modes, mi->num_modes, &info->modelist); in pxa168fb_probe()
698 ret = pxa168fb_check_var(&info->var, info); in pxa168fb_probe()
705 clk_prepare_enable(fbi->clk); in pxa168fb_probe()
712 writel(0, fbi->reg_base + LCD_SPU_BLANKCOLOR); in pxa168fb_probe()
713 writel(mi->io_pin_allocation_mode, fbi->reg_base + SPU_IOPAD_CONTROL); in pxa168fb_probe()
714 writel(0, fbi->reg_base + LCD_CFG_GRA_START_ADDR1); in pxa168fb_probe()
715 writel(0, fbi->reg_base + LCD_SPU_GRA_OVSA_HPXL_VLN); in pxa168fb_probe()
716 writel(0, fbi->reg_base + LCD_SPU_SRAM_PARA0); in pxa168fb_probe()
718 fbi->reg_base + LCD_SPU_SRAM_PARA1); in pxa168fb_probe()
723 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) { in pxa168fb_probe()
724 ret = -ENOMEM; in pxa168fb_probe()
731 ret = devm_request_irq(&pdev->dev, irq, pxa168fb_handle_irq, in pxa168fb_probe()
732 IRQF_SHARED, info->fix.id, fbi); in pxa168fb_probe()
734 dev_err(&pdev->dev, "unable to request IRQ\n"); in pxa168fb_probe()
735 ret = -ENXIO; in pxa168fb_probe()
742 writel(GRA_FRAME_IRQ0_ENA(0x1), fbi->reg_base + SPU_IRQ_ENA); in pxa168fb_probe()
749 dev_err(&pdev->dev, "Failed to register pxa168-fb: %d\n", ret); in pxa168fb_probe()
750 ret = -ENXIO; in pxa168fb_probe()
758 fb_dealloc_cmap(&info->cmap); in pxa168fb_probe()
760 clk_disable_unprepare(fbi->clk); in pxa168fb_probe()
762 dma_free_wc(fbi->dev, info->fix.smem_len, in pxa168fb_probe()
763 info->screen_base, fbi->fb_start_dma); in pxa168fb_probe()
767 dev_err(&pdev->dev, "frame buffer device init failed with %d\n", ret); in pxa168fb_probe()
781 data = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0); in pxa168fb_remove()
783 writel(data, fbi->reg_base + LCD_SPU_DMA_CTRL0); in pxa168fb_remove()
785 info = fbi->info; in pxa168fb_remove()
789 writel(GRA_FRAME_IRQ0_ENA(0x0), fbi->reg_base + SPU_IRQ_ENA); in pxa168fb_remove()
791 if (info->cmap.len) in pxa168fb_remove()
792 fb_dealloc_cmap(&info->cmap); in pxa168fb_remove()
794 dma_free_wc(fbi->dev, info->fix.smem_len, in pxa168fb_remove()
795 info->screen_base, info->fix.smem_start); in pxa168fb_remove()
797 clk_disable_unprepare(fbi->clk); in pxa168fb_remove()
806 .name = "pxa168-fb",