Lines Matching full:dss
3 * linux/drivers/video/omap2/dss/dss.c
12 #define DSS_SUBSYS_NAME "DSS"
36 #include "dss.h"
95 } dss; variable
115 __raw_writel(val, dss.base + idx.idx); in dss_write_reg()
120 return __raw_readl(dss.base + idx.idx); in dss_read_reg()
124 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
126 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
140 dss.ctx_valid = true; in dss_save_context()
149 if (!dss.ctx_valid) in dss_restore_context()
171 if (!dss.syscon_pll_ctrl) in dss_ctrl_pll_enable()
187 DSSERR("illegal DSS PLL ID %d\n", pll_id); in dss_ctrl_pll_enable()
191 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, in dss_ctrl_pll_enable()
200 if (!dss.syscon_pll_ctrl) in dss_ctrl_pll_set_control_mux()
255 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, in dss_ctrl_pll_set_control_mux()
359 seq_printf(s, "- DSS -\n"); in dss_dump_clocks()
363 fclk_rate = clk_get_rate(dss.dss_clk); in dss_dump_clocks()
419 dss.dispc_clk_source = clk_src; in dss_select_dispc_clk_source()
447 dss.dsi_clk_source[dsi_module] = clk_src; in dss_select_dsi_clk_source()
484 dss.lcd_clk_source[ix] = clk_src; in dss_select_lcd_clk_source()
489 return dss.dispc_clk_source; in dss_get_dispc_clk_source()
494 return dss.dsi_clk_source[dsi_module]; in dss_get_dsi_clk_source()
502 return dss.lcd_clk_source[ix]; in dss_get_lcd_clk_source()
506 return dss.dispc_clk_source; in dss_get_lcd_clk_source()
522 if (dss.parent_clk == NULL) { in dss_div_calc()
529 fck = clk_round_rate(dss.dss_clk, fck); in dss_div_calc()
534 fckd_hw_max = dss.feat->fck_div_max; in dss_div_calc()
536 m = dss.feat->dss_fck_multiplier; in dss_div_calc()
537 prate = clk_get_rate(dss.parent_clk); in dss_div_calc()
560 r = clk_set_rate(dss.dss_clk, rate); in dss_set_fck_rate()
564 dss.dss_clk_rate = clk_get_rate(dss.dss_clk); in dss_set_fck_rate()
566 WARN_ONCE(dss.dss_clk_rate != rate, in dss_set_fck_rate()
567 "clk rate mismatch: %lu != %lu", dss.dss_clk_rate, in dss_set_fck_rate()
575 return dss.dss_clk_rate; in dss_get_dispc_clk_rate()
587 if (dss.parent_clk == NULL) { in dss_setup_default_clock()
588 fck = clk_round_rate(dss.dss_clk, max_dss_fck); in dss_setup_default_clock()
590 prate = clk_get_rate(dss.parent_clk); in dss_setup_default_clock()
592 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, in dss_setup_default_clock()
594 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier; in dss_setup_default_clock()
728 return dss.feat->dpi_select_source(port, channel); in dss_dpi_select_source()
735 clk = devm_clk_get(&dss.pdev->dev, "fck"); in dss_get_clocks()
741 dss.dss_clk = clk; in dss_get_clocks()
743 if (dss.feat->parent_clk_name) { in dss_get_clocks()
744 clk = clk_get(NULL, dss.feat->parent_clk_name); in dss_get_clocks()
746 DSSERR("Failed to get %s\n", dss.feat->parent_clk_name); in dss_get_clocks()
753 dss.parent_clk = clk; in dss_get_clocks()
760 if (dss.parent_clk) in dss_put_clocks()
761 clk_put(dss.parent_clk); in dss_put_clocks()
770 r = pm_runtime_get_sync(&dss.pdev->dev); in dss_runtime_get()
772 pm_runtime_put_sync(&dss.pdev->dev); in dss_runtime_get()
784 r = pm_runtime_put_sync(&dss.pdev->dev); in dss_runtime_put()
931 if (dss.feat->num_ports == 0) in dss_init_ports()
942 if (reg >= dss.feat->num_ports) in dss_init_ports()
945 port_type = dss.feat->ports[reg]; in dss_init_ports()
978 if (dss.feat->num_ports == 0) in dss_uninit_ports()
990 if (reg >= dss.feat->num_ports) in dss_uninit_ports()
993 port_type = dss.feat->ports[reg]; in dss_uninit_ports()
1018 dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np, in dss_video_pll_probe()
1020 if (IS_ERR(dss.syscon_pll_ctrl)) { in dss_video_pll_probe()
1023 return PTR_ERR(dss.syscon_pll_ctrl); in dss_video_pll_probe()
1027 &dss.syscon_pll_ctrl_offset)) { in dss_video_pll_probe()
1053 dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator); in dss_video_pll_probe()
1054 if (IS_ERR(dss.video1_pll)) in dss_video_pll_probe()
1055 return PTR_ERR(dss.video1_pll); in dss_video_pll_probe()
1059 dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator); in dss_video_pll_probe()
1060 if (IS_ERR(dss.video2_pll)) { in dss_video_pll_probe()
1061 dss_video_pll_uninit(dss.video1_pll); in dss_video_pll_probe()
1062 return PTR_ERR(dss.video2_pll); in dss_video_pll_probe()
1069 /* DSS HW IP initialisation */
1077 dss.pdev = pdev; in dss_bind()
1079 dss.feat = dss_get_features(); in dss_bind()
1080 if (!dss.feat) in dss_bind()
1083 dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); in dss_bind()
1085 DSSERR("can't get IORESOURCE_MEM DSS\n"); in dss_bind()
1089 dss.base = devm_ioremap(&pdev->dev, dss_mem->start, in dss_bind()
1091 if (!dss.base) { in dss_bind()
1092 DSSERR("can't ioremap DSS\n"); in dss_bind()
1118 dss.dss_clk_rate = clk_get_rate(dss.dss_clk); in dss_bind()
1130 dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; in dss_bind()
1131 dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; in dss_bind()
1132 dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; in dss_bind()
1133 dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; in dss_bind()
1134 dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; in dss_bind()
1137 printk(KERN_INFO "OMAP DSS rev %d.%d\n", in dss_bind()
1146 dss_debugfs_create_file("dss", dss_dump_regs); in dss_bind()
1159 if (dss.video1_pll) in dss_bind()
1160 dss_video_pll_uninit(dss.video1_pll); in dss_bind()
1162 if (dss.video2_pll) in dss_bind()
1163 dss_video_pll_uninit(dss.video2_pll); in dss_bind()
1178 if (dss.video1_pll) in dss_unbind()
1179 dss_video_pll_uninit(dss.video1_pll); in dss_unbind()
1181 if (dss.video2_pll) in dss_unbind()
1182 dss_video_pll_uninit(dss.video2_pll); in dss_unbind()
1209 * Otherwise dss will never get probed successfully, as it will wait in dss_add_child_component()
1278 { .compatible = "ti,omap2-dss", },
1279 { .compatible = "ti,omap3-dss", },
1280 { .compatible = "ti,omap4-dss", },
1281 { .compatible = "ti,omap5-dss", },
1282 { .compatible = "ti,dra7-dss", },