Lines Matching +full:0 +full:x58
64 #define AVIVO_DC_LUT_RW_SELECT 0x6480
65 #define AVIVO_DC_LUT_RW_MODE 0x6484
66 #define AVIVO_DC_LUT_RW_INDEX 0x6488
67 #define AVIVO_DC_LUT_SEQ_COLOR 0x648c
68 #define AVIVO_DC_LUT_PWL_DATA 0x6490
69 #define AVIVO_DC_LUT_30_COLOR 0x6494
70 #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
71 #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
72 #define AVIVO_DC_LUT_AUTOFILL 0x64a0
74 #define AVIVO_DC_LUTA_CONTROL 0x64c0
75 #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
76 #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
77 #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
78 #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
79 #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
80 #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
82 #define AVIVO_DC_LUTB_CONTROL 0x6cc0
83 #define AVIVO_DC_LUTB_BLACK_OFFSET_BLUE 0x6cc4
84 #define AVIVO_DC_LUTB_BLACK_OFFSET_GREEN 0x6cc8
85 #define AVIVO_DC_LUTB_BLACK_OFFSET_RED 0x6ccc
86 #define AVIVO_DC_LUTB_WHITE_OFFSET_BLUE 0x6cd0
87 #define AVIVO_DC_LUTB_WHITE_OFFSET_GREEN 0x6cd4
88 #define AVIVO_DC_LUTB_WHITE_OFFSET_RED 0x6cd8
93 * entries in the var structure). Return != 0 for invalid regno.
114 if (info->var.transp.length > 0) { in offb_setcolreg()
120 return 0; in offb_setcolreg()
131 return 0; in offb_setcolreg()
142 out_le32(par->cmap_adr + 0x58, in offb_setcolreg()
143 in_le32(par->cmap_adr + 0x58) & ~0x20); in offb_setcolreg()
147 out_8(par->cmap_adr + 0xb0, regno); in offb_setcolreg()
148 out_le32(par->cmap_adr + 0xb4, in offb_setcolreg()
153 out_le32(par->cmap_adr + 0x58, in offb_setcolreg()
154 in_le32(par->cmap_adr + 0x58) | 0x20); in offb_setcolreg()
156 out_8(par->cmap_adr + 0xb0, regno); in offb_setcolreg()
157 out_le32(par->cmap_adr + 0xb4, (red << 16 | green << 8 | blue)); in offb_setcolreg()
161 out_8(par->cmap_adr + 0xb0, regno); in offb_setcolreg()
162 out_le32(par->cmap_adr + 0xb4, (red << 16 | green << 8 | blue)); in offb_setcolreg()
174 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); in offb_setcolreg()
181 return 0; in offb_setcolreg()
194 return 0; in offb_blank()
198 return 0; in offb_blank()
203 for (i = 0; i < 256; i++) { in offb_blank()
207 for (j = 0; j < 3; j++) in offb_blank()
208 writeb(0, par->cmap_data); in offb_blank()
212 out_le32(par->cmap_adr + 0x58, in offb_blank()
213 in_le32(par->cmap_adr + 0x58) & ~0x20); in offb_blank()
217 out_8(par->cmap_adr + 0xb0, i); in offb_blank()
218 out_le32(par->cmap_adr + 0xb4, 0); in offb_blank()
222 out_le32(par->cmap_adr + 0x58, in offb_blank()
223 in_le32(par->cmap_adr + 0x58) | 0x20); in offb_blank()
225 out_8(par->cmap_adr + 0xb0, i); in offb_blank()
226 out_le32(par->cmap_adr + 0xb4, 0); in offb_blank()
229 out_8(par->cmap_adr + 0xb0, i); in offb_blank()
230 out_le32(par->cmap_adr + 0xb4, 0); in offb_blank()
234 0); in offb_blank()
239 writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR); in offb_blank()
240 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); in offb_blank()
242 writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR); in offb_blank()
247 return 0; in offb_blank()
256 writel(0, par->cmap_adr + AVIVO_DC_LUTA_CONTROL); in offb_set_par()
257 writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_BLUE); in offb_set_par()
258 writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_GREEN); in offb_set_par()
259 writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_RED); in offb_set_par()
260 writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_BLUE); in offb_set_par()
261 writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_GREEN); in offb_set_par()
262 writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_RED); in offb_set_par()
263 writel(0, par->cmap_adr + AVIVO_DC_LUTB_CONTROL); in offb_set_par()
264 writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_BLUE); in offb_set_par()
265 writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_GREEN); in offb_set_par()
266 writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_RED); in offb_set_par()
267 writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_BLUE); in offb_set_par()
268 writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_GREEN); in offb_set_par()
269 writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_RED); in offb_set_par()
271 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_MODE); in offb_set_par()
272 writel(0x0000003f, par->cmap_adr + AVIVO_DC_LUT_WRITE_EN_MASK); in offb_set_par()
273 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); in offb_set_par()
274 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_MODE); in offb_set_par()
275 writel(0x0000003f, par->cmap_adr + AVIVO_DC_LUT_WRITE_EN_MASK); in offb_set_par()
277 return 0; in offb_set_par()
284 release_mem_region(info->apertures->ranges[0].base, info->apertures->ranges[0].size); in offb_destroy()
312 if ((flags & (IORESOURCE_IO | IORESOURCE_MEM)) == 0) in offb_map_reg()
328 par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff); in offb_init_palette_hacks()
333 par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff); in offb_init_palette_hacks()
337 par->cmap_adr = offb_map_reg(dp, 2, 0, 0x1fff); in offb_init_palette_hacks()
341 par->cmap_adr = offb_map_reg(dp, 1, 0, 0x1fff); in offb_init_palette_hacks()
345 unsigned long base = address & 0xff000000UL; in offb_init_palette_hacks()
347 ioremap(base + 0x7ff000, 0x1000) + 0xcc0; in offb_init_palette_hacks()
352 par->cmap_adr = offb_map_reg(dp, 0, 0x6000, 0x1000); in offb_init_palette_hacks()
362 if (vid && did && *vid == 0x1002 && in offb_init_palette_hacks()
363 ((*did >= 0x7100 && *did < 0x7800) || in offb_init_palette_hacks()
364 (*did >= 0x9400))) { in offb_init_palette_hacks()
365 par->cmap_adr = offb_map_reg(pciparent, 2, 0, 0x10000); in offb_init_palette_hacks()
372 const __be32 io_of_addr[3] = { 0x01000000, 0x0, 0x0 }; in offb_init_palette_hacks()
374 const __be32 io_of_addr[3] = { 0x00000001, 0x0, 0x0 }; in offb_init_palette_hacks()
378 par->cmap_adr = ioremap(io_addr + 0x3c8, 2); in offb_init_palette_hacks()
415 if (info == 0) { in offb_init_fb()
427 fix->id[sizeof(fix->id) - 1] = '\0'; in offb_init_fb()
439 fix->type_aux = 0; in offb_init_fb()
447 var->xoffset = var->yoffset = 0; in offb_init_fb()
451 var->red.offset = 0; in offb_init_fb()
453 var->green.offset = 0; in offb_init_fb()
455 var->blue.offset = 0; in offb_init_fb()
457 var->transp.offset = 0; in offb_init_fb()
458 var->transp.length = 0; in offb_init_fb()
466 var->blue.offset = 0; in offb_init_fb()
468 var->transp.offset = 0; in offb_init_fb()
469 var->transp.length = 0; in offb_init_fb()
477 var->blue.offset = 0; in offb_init_fb()
479 var->transp.offset = 0; in offb_init_fb()
480 var->transp.length = 0; in offb_init_fb()
488 var->blue.offset = 0; in offb_init_fb()
495 var->transp.msb_right = 0; in offb_init_fb()
496 var->grayscale = 0; in offb_init_fb()
497 var->nonstd = 0; in offb_init_fb()
498 var->activate = 0; in offb_init_fb()
504 var->sync = 0; in offb_init_fb()
511 info->apertures->ranges[0].base = address; in offb_init_fb()
512 info->apertures->ranges[0].size = fix->smem_len; in offb_init_fb()
519 fb_alloc_cmap(&info->cmap, 256, 0); in offb_init_fb()
521 if (register_framebuffer(info) < 0) in offb_init_fb()
542 unsigned int flags, rsize, addr_prop = 0; in offb_init_nodriver()
543 unsigned long max_size = 0; in offb_init_nodriver()
547 int foreign_endian = 0; in offb_init_nodriver()
578 if (pp && len == sizeof(u32) && (*pp != 0xffffffffu)) in offb_init_nodriver()
605 for (i = 0; (addrp = of_get_address(dp, i, &asize, &flags)) in offb_init_nodriver()
607 int match_addrp = 0; in offb_init_nodriver()
652 address += 0x1000; in offb_init_nodriver()
681 offb_init_nodriver(dp, 0); in offb_init()
687 offb_init_nodriver(dp, 0); in offb_init()
690 return 0; in offb_init()