Lines Matching +full:standard +full:- +full:vt
1 // SPDX-License-Identifier: GPL-2.0-only
6 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
33 * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
57 * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
79 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
108 unsigned int pixclock = var->pixclock; in matroxfb_var2my()
113 mt->pixclock = 1000000000 / pixclock; in matroxfb_var2my()
114 if (mt->pixclock < 1) mt->pixclock = 1; in matroxfb_var2my()
115 mt->mnp = -1; in matroxfb_var2my()
116 mt->dblscan = var->vmode & FB_VMODE_DOUBLE; in matroxfb_var2my()
117 mt->interlaced = var->vmode & FB_VMODE_INTERLACED; in matroxfb_var2my()
118 mt->HDisplay = var->xres; in matroxfb_var2my()
119 mt->HSyncStart = mt->HDisplay + var->right_margin; in matroxfb_var2my()
120 mt->HSyncEnd = mt->HSyncStart + var->hsync_len; in matroxfb_var2my()
121 mt->HTotal = mt->HSyncEnd + var->left_margin; in matroxfb_var2my()
122 mt->VDisplay = var->yres; in matroxfb_var2my()
123 mt->VSyncStart = mt->VDisplay + var->lower_margin; in matroxfb_var2my()
124 mt->VSyncEnd = mt->VSyncStart + var->vsync_len; in matroxfb_var2my()
125 mt->VTotal = mt->VSyncEnd + var->upper_margin; in matroxfb_var2my()
126 mt->sync = var->sync; in matroxfb_var2my()
133 unsigned int fxtal = pll->ref_freq; in matroxfb_PLL_calcclock()
142 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max); in matroxfb_PLL_calcclock()
143 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq); in matroxfb_PLL_calcclock()
145 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min); in matroxfb_PLL_calcclock()
146 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min); in matroxfb_PLL_calcclock()
147 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max); in matroxfb_PLL_calcclock()
148 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min); in matroxfb_PLL_calcclock()
149 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max); in matroxfb_PLL_calcclock()
152 for (p = 1; p <= pll->post_shift_max; p++) { in matroxfb_PLL_calcclock()
157 if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min; in matroxfb_PLL_calcclock()
159 for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) { in matroxfb_PLL_calcclock()
162 if (fwant < pll->vco_freq_min) break; in matroxfb_PLL_calcclock()
163 for (m = pll->in_div_min; m <= pll->in_div_max; m++) { in matroxfb_PLL_calcclock()
167 n = (fwant * (m + 1) + (fxtal >> 1)) / fxtal - 1; in matroxfb_PLL_calcclock()
168 if (n > pll->feed_div_max) in matroxfb_PLL_calcclock()
170 if (n < pll->feed_div_min) in matroxfb_PLL_calcclock()
171 n = pll->feed_div_min; in matroxfb_PLL_calcclock()
174 diff = fwant - fvco; in matroxfb_PLL_calcclock()
176 diff = fvco - fwant; in matroxfb_PLL_calcclock()
193 unsigned int vd, vs, ve, vt, lc; in matroxfb_vgaHWinit() local
197 struct matrox_hw_state * const hw = &minfo->hw; in matroxfb_vgaHWinit()
201 hw->SEQ[0] = 0x00; in matroxfb_vgaHWinit()
202 hw->SEQ[1] = 0x01; /* or 0x09 */ in matroxfb_vgaHWinit()
203 hw->SEQ[2] = 0x0F; /* bitplanes */ in matroxfb_vgaHWinit()
204 hw->SEQ[3] = 0x00; in matroxfb_vgaHWinit()
205 hw->SEQ[4] = 0x0E; in matroxfb_vgaHWinit()
207 if (m->dblscan) { in matroxfb_vgaHWinit()
208 m->VTotal <<= 1; in matroxfb_vgaHWinit()
209 m->VDisplay <<= 1; in matroxfb_vgaHWinit()
210 m->VSyncStart <<= 1; in matroxfb_vgaHWinit()
211 m->VSyncEnd <<= 1; in matroxfb_vgaHWinit()
213 if (m->interlaced) { in matroxfb_vgaHWinit()
214 m->VTotal >>= 1; in matroxfb_vgaHWinit()
215 m->VDisplay >>= 1; in matroxfb_vgaHWinit()
216 m->VSyncStart >>= 1; in matroxfb_vgaHWinit()
217 m->VSyncEnd >>= 1; in matroxfb_vgaHWinit()
221 hw->GCTL[0] = 0x00; in matroxfb_vgaHWinit()
222 hw->GCTL[1] = 0x00; in matroxfb_vgaHWinit()
223 hw->GCTL[2] = 0x00; in matroxfb_vgaHWinit()
224 hw->GCTL[3] = 0x00; in matroxfb_vgaHWinit()
225 hw->GCTL[4] = 0x00; in matroxfb_vgaHWinit()
226 hw->GCTL[5] = 0x40; in matroxfb_vgaHWinit()
227 hw->GCTL[6] = 0x05; in matroxfb_vgaHWinit()
228 hw->GCTL[7] = 0x0F; in matroxfb_vgaHWinit()
229 hw->GCTL[8] = 0xFF; in matroxfb_vgaHWinit()
233 hw->ATTR[i] = i; in matroxfb_vgaHWinit()
234 hw->ATTR[16] = 0x41; in matroxfb_vgaHWinit()
235 hw->ATTR[17] = 0xFF; in matroxfb_vgaHWinit()
236 hw->ATTR[18] = 0x0F; in matroxfb_vgaHWinit()
237 hw->ATTR[19] = 0x00; in matroxfb_vgaHWinit()
238 hw->ATTR[20] = 0x00; in matroxfb_vgaHWinit()
240 hd = m->HDisplay >> 3; in matroxfb_vgaHWinit()
241 hs = m->HSyncStart >> 3; in matroxfb_vgaHWinit()
242 he = m->HSyncEnd >> 3; in matroxfb_vgaHWinit()
243 ht = m->HTotal >> 3; in matroxfb_vgaHWinit()
244 /* standard timmings are in 8pixels, but for interleaved we cannot */ in matroxfb_vgaHWinit()
247 divider = minfo->curr.final_bppShift; in matroxfb_vgaHWinit()
264 hd = hd - 1; in matroxfb_vgaHWinit()
265 hs = hs - 1; in matroxfb_vgaHWinit()
266 he = he - 1; in matroxfb_vgaHWinit()
267 ht = ht - 1; in matroxfb_vgaHWinit()
268 vd = m->VDisplay - 1; in matroxfb_vgaHWinit()
269 vs = m->VSyncStart - 1; in matroxfb_vgaHWinit()
270 ve = m->VSyncEnd - 1; in matroxfb_vgaHWinit()
271 vt = m->VTotal - 2; in matroxfb_vgaHWinit()
277 wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64; in matroxfb_vgaHWinit()
279 hw->CRTCEXT[0] = 0; in matroxfb_vgaHWinit()
280 hw->CRTCEXT[5] = 0; in matroxfb_vgaHWinit()
281 if (m->interlaced) { in matroxfb_vgaHWinit()
282 hw->CRTCEXT[0] = 0x80; in matroxfb_vgaHWinit()
283 hw->CRTCEXT[5] = (hs + he - ht) >> 1; in matroxfb_vgaHWinit()
284 if (!m->dblscan) in matroxfb_vgaHWinit()
286 vt &= ~1; in matroxfb_vgaHWinit()
288 hw->CRTCEXT[0] |= (wd & 0x300) >> 4; in matroxfb_vgaHWinit()
289 hw->CRTCEXT[1] = (((ht - 4) & 0x100) >> 8) | in matroxfb_vgaHWinit()
293 /* FIXME: Enable vidrst only on G400, and only if TV-out is used */ in matroxfb_vgaHWinit()
294 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1) in matroxfb_vgaHWinit()
295 hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */ in matroxfb_vgaHWinit()
296 hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) | in matroxfb_vgaHWinit()
301 hw->CRTCEXT[3] = (divider - 1) | 0x80; in matroxfb_vgaHWinit()
302 hw->CRTCEXT[4] = 0; in matroxfb_vgaHWinit()
304 hw->CRTC[0] = ht-4; in matroxfb_vgaHWinit()
305 hw->CRTC[1] = hd; in matroxfb_vgaHWinit()
306 hw->CRTC[2] = hd; in matroxfb_vgaHWinit()
307 hw->CRTC[3] = (hbe & 0x1F) | 0x80; in matroxfb_vgaHWinit()
308 hw->CRTC[4] = hs; in matroxfb_vgaHWinit()
309 hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F); in matroxfb_vgaHWinit()
310 hw->CRTC[6] = vt & 0xFF; in matroxfb_vgaHWinit()
311 hw->CRTC[7] = ((vt & 0x100) >> 8) | in matroxfb_vgaHWinit()
316 ((vt & 0x200) >> 4) | in matroxfb_vgaHWinit()
319 hw->CRTC[8] = 0x00; in matroxfb_vgaHWinit()
320 hw->CRTC[9] = ((vd & 0x200) >> 4) | in matroxfb_vgaHWinit()
322 if (m->dblscan && !m->interlaced) in matroxfb_vgaHWinit()
323 hw->CRTC[9] |= 0x80; in matroxfb_vgaHWinit()
325 hw->CRTC[i] = 0x00; in matroxfb_vgaHWinit()
326 hw->CRTC[16] = vs /* & 0xFF */; in matroxfb_vgaHWinit()
327 hw->CRTC[17] = (ve & 0x0F) | 0x20; in matroxfb_vgaHWinit()
328 hw->CRTC[18] = vd /* & 0xFF */; in matroxfb_vgaHWinit()
329 hw->CRTC[19] = wd /* & 0xFF */; in matroxfb_vgaHWinit()
330 hw->CRTC[20] = 0x00; in matroxfb_vgaHWinit()
331 hw->CRTC[21] = vd /* & 0xFF */; in matroxfb_vgaHWinit()
332 hw->CRTC[22] = (vt + 1) /* & 0xFF */; in matroxfb_vgaHWinit()
333 hw->CRTC[23] = 0xC3; in matroxfb_vgaHWinit()
334 hw->CRTC[24] = lc; in matroxfb_vgaHWinit()
341 struct matrox_hw_state * const hw = &minfo->hw; in matroxfb_vgaHWrestore()
346 dprintk(KERN_INFO "MiscOutReg: %02X\n", hw->MiscOutReg); in matroxfb_vgaHWrestore()
349 dprintk("%02X:", hw->SEQ[i]); in matroxfb_vgaHWrestore()
353 dprintk("%02X:", hw->GCTL[i]); in matroxfb_vgaHWrestore()
357 dprintk("%02X:", hw->CRTC[i]); in matroxfb_vgaHWrestore()
361 dprintk("%02X:", hw->ATTR[i]); in matroxfb_vgaHWrestore()
368 mga_outb(M_MISC_REG, hw->MiscOutReg); in matroxfb_vgaHWrestore()
370 mga_setr(M_SEQ_INDEX, i, hw->SEQ[i]); in matroxfb_vgaHWrestore()
371 mga_setr(M_CRTC_INDEX, 17, hw->CRTC[17] & 0x7F); in matroxfb_vgaHWrestore()
373 mga_setr(M_CRTC_INDEX, i, hw->CRTC[i]); in matroxfb_vgaHWrestore()
375 mga_setr(M_GRAPHICS_INDEX, i, hw->GCTL[i]); in matroxfb_vgaHWrestore()
379 mga_outb(M_ATTR_INDEX, hw->ATTR[i]); in matroxfb_vgaHWrestore()
384 mga_outb(M_DAC_VAL, hw->DACpal[i]); in matroxfb_vgaHWrestore()
398 unsigned char* dst = bd->pins; in get_pins()
413 bd->pins_len = pins_len; in get_pins()
416 unsigned char* dst = bd->pins; in get_pins()
423 bd->pins_len = 0x40; in get_pins()
439 bd->version.vMaj = (h >> 4) & 0xF; in get_bios_version()
440 bd->version.vMin = h & 0xF; in get_bios_version()
441 bd->version.vRev = readb(vbios + pcir_offset + 0x13); in get_bios_version()
446 bd->version.vMaj = (h >> 4) & 0xF; in get_bios_version()
447 bd->version.vMin = h & 0xF; in get_bios_version()
448 bd->version.vRev = 0; in get_bios_version()
459 bd->output.state = b; in get_bios_output()
465 /* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */ in get_bios_tvout()
466 bd->output.tvout = 0; in get_bios_tvout()
480 bd->output.tvout = 1; in get_bios_tvout()
495 bd->bios_valid = 1; in parse_bios()
535 switch (bd->pins[22]) { in parse_pins1()
540 if (get_unaligned_le16(bd->pins + 24)) { in parse_pins1()
541 maxdac = get_unaligned_le16(bd->pins + 24) * 10; in parse_pins1()
543 minfo->limits.pixel.vcomax = maxdac; in parse_pins1()
544 minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ? in parse_pins1()
545 get_unaligned_le16(bd->pins + 28) * 10 : 50000; in parse_pins1()
547 minfo->features.pll.ref_freq = 14318; in parse_pins1()
548 minfo->values.reg.mctlwtst = 0x00030101; in parse_pins1()
555 minfo->limits.pixel.vcomax = 220000; in default_pins1()
556 minfo->values.pll.system = 50000; in default_pins1()
557 minfo->features.pll.ref_freq = 14318; in default_pins1()
558 minfo->values.reg.mctlwtst = 0x00030101; in default_pins1()
564 minfo->limits.pixel.vcomax = in parse_pins2()
565 minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000); in parse_pins2()
566 minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) | in parse_pins2()
567 ((bd->pins[51] & 0x02) ? 0x00000100 : 0) | in parse_pins2()
568 ((bd->pins[51] & 0x04) ? 0x00010000 : 0) | in parse_pins2()
569 ((bd->pins[51] & 0x08) ? 0x00020000 : 0); in parse_pins2()
570 minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000); in parse_pins2()
571 minfo->features.pll.ref_freq = 14318; in parse_pins2()
578 minfo->limits.pixel.vcomax = in default_pins2()
579 minfo->limits.system.vcomax = 230000; in default_pins2()
580 minfo->values.reg.mctlwtst = 0x00030101; in default_pins2()
581 minfo->values.pll.system = 50000; in default_pins2()
582 minfo->features.pll.ref_freq = 14318; in default_pins2()
588 minfo->limits.pixel.vcomax = in parse_pins3()
589 minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000); in parse_pins3()
590 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ? in parse_pins3()
591 0x01250A21 : get_unaligned_le32(bd->pins + 48); in parse_pins3()
593 minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) | in parse_pins3()
594 ((bd->pins[57] << 22) & 0x00C00000) | in parse_pins3()
595 ((bd->pins[56] << 1) & 0x000001E0) | in parse_pins3()
596 ( bd->pins[56] & 0x0000000F); in parse_pins3()
597 minfo->values.reg.opt = (bd->pins[54] & 7) << 10; in parse_pins3()
598 minfo->values.reg.opt2 = bd->pins[58] << 12; in parse_pins3()
599 minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000; in parse_pins3()
606 minfo->limits.pixel.vcomax = in default_pins3()
607 minfo->limits.system.vcomax = 230000; in default_pins3()
608 minfo->values.reg.mctlwtst = 0x01250A21; in default_pins3()
609 minfo->values.reg.memrdbk = 0x00000000; in default_pins3()
610 minfo->values.reg.opt = 0x00000C00; in default_pins3()
611 minfo->values.reg.opt2 = 0x00000000; in default_pins3()
612 minfo->features.pll.ref_freq = 27000; in default_pins3()
618 minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000; in parse_pins4()
619 …minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38]… in parse_pins4()
620 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71); in parse_pins4()
621 minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) | in parse_pins4()
622 ((bd->pins[87] << 22) & 0x00C00000) | in parse_pins4()
623 ((bd->pins[86] << 1) & 0x000001E0) | in parse_pins4()
624 ( bd->pins[86] & 0x0000000F); in parse_pins4()
625 minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) | in parse_pins4()
626 ((bd->pins[53] << 22) & 0x10000000) | in parse_pins4()
627 ((bd->pins[53] << 7) & 0x00001C00); in parse_pins4()
628 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67); in parse_pins4()
629 minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000; in parse_pins4()
630 minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000; in parse_pins4()
637 minfo->limits.pixel.vcomax = in default_pins4()
638 minfo->limits.system.vcomax = 252000; in default_pins4()
639 minfo->values.reg.mctlwtst = 0x04A450A1; in default_pins4()
640 minfo->values.reg.memrdbk = 0x000000E7; in default_pins4()
641 minfo->values.reg.opt = 0x10000400; in default_pins4()
642 minfo->values.reg.opt3 = 0x0190A419; in default_pins4()
643 minfo->values.pll.system = 200000; in default_pins4()
644 minfo->features.pll.ref_freq = 27000; in default_pins4()
652 mult = bd->pins[4]?8000:6000; in parse_pins5()
654 minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult; in parse_pins5()
655 …minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36]… in parse_pins5()
656 …minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37]… in parse_pins5()
657 minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult; in parse_pins5()
658 …minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121]… in parse_pins5()
659 …minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122]… in parse_pins5()
660 minfo->values.pll.system = in parse_pins5()
661 minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000; in parse_pins5()
662 minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48); in parse_pins5()
663 minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52); in parse_pins5()
664 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94); in parse_pins5()
665 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98); in parse_pins5()
666 minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102); in parse_pins5()
667 minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106); in parse_pins5()
668 minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000; in parse_pins5()
669 minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20; in parse_pins5()
670 minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0; in parse_pins5()
671 minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0; in parse_pins5()
672 minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000; in parse_pins5()
673 if (bd->pins[115] & 4) { in parse_pins5()
674 minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst; in parse_pins5()
680 minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) | in parse_pins5()
681 wtst_xlat[minfo->values.reg.mctlwtst & 7]; in parse_pins5()
683 minfo->max_pixel_clock_panellink = bd->pins[47] * 4000; in parse_pins5()
690 minfo->limits.pixel.vcomax = in default_pins5()
691 minfo->limits.system.vcomax = in default_pins5()
692 minfo->limits.video.vcomax = 600000; in default_pins5()
693 minfo->limits.pixel.vcomin = in default_pins5()
694 minfo->limits.system.vcomin = in default_pins5()
695 minfo->limits.video.vcomin = 256000; in default_pins5()
696 minfo->values.pll.system = in default_pins5()
697 minfo->values.pll.video = 284000; in default_pins5()
698 minfo->values.reg.opt = 0x404A1160; in default_pins5()
699 minfo->values.reg.opt2 = 0x0000AC00; in default_pins5()
700 minfo->values.reg.opt3 = 0x0090A409; in default_pins5()
701 minfo->values.reg.mctlwtst_core = in default_pins5()
702 minfo->values.reg.mctlwtst = 0x0C81462B; in default_pins5()
703 minfo->values.reg.memmisc = 0x80000004; in default_pins5()
704 minfo->values.reg.memrdbk = 0x01001103; in default_pins5()
705 minfo->features.pll.ref_freq = 27000; in default_pins5()
706 minfo->values.memory.ddr = 1; in default_pins5()
707 minfo->values.memory.dll = 1; in default_pins5()
708 minfo->values.memory.emrswen = 1; in default_pins5()
709 minfo->values.reg.maccess = 0x00004000; in default_pins5()
718 switch (minfo->chip) { in matroxfb_set_limits()
729 if (!bd->bios_valid) { in matroxfb_set_limits()
731 return -1; in matroxfb_set_limits()
733 if (bd->pins_len < 64) { in matroxfb_set_limits()
735 return -1; in matroxfb_set_limits()
737 if (bd->pins[0] == 0x2E && bd->pins[1] == 0x41) { in matroxfb_set_limits()
738 pins_version = bd->pins[5]; in matroxfb_set_limits()
741 return -1; in matroxfb_set_limits()
746 if (bd->pins_len != pinslen[pins_version - 1]) { in matroxfb_set_limits()
748 return -1; in matroxfb_set_limits()
763 return -1; in matroxfb_set_limits()
772 struct pci_dev *pdev = minfo->pcidev; in matroxfb_read_pins()
774 memset(&minfo->bios, 0, sizeof(minfo->bios)); in matroxfb_read_pins()
778 pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase); in matroxfb_read_pins()
780 parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios); in matroxfb_read_pins()
784 if (!minfo->bios.bios_valid) { in matroxfb_read_pins()
794 if (ven != pdev->vendor || dev != pdev->device) { in matroxfb_read_pins()
796 ven, dev, pdev->vendor, pdev->device); in matroxfb_read_pins()
798 parse_bios(b, &minfo->bios); in matroxfb_read_pins()
804 matroxfb_set_limits(minfo, &minfo->bios); in matroxfb_read_pins()
806 (minfo->values.reg.opt & 0x1C00) >> 10); in matroxfb_read_pins()
817 MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");