286 	if (INREG(LVDS) & PORT_ENABLE)  in intelfbhw_check_non_crt()
288 	if (INREG(DVOA) & PORT_ENABLE)  in intelfbhw_check_non_crt()
290 	if (INREG(DVOB) & PORT_ENABLE)  in intelfbhw_check_non_crt()
292 	if (INREG(DVOC) & PORT_ENABLE)  in intelfbhw_check_non_crt()
427 	tmp = INREG(DSPACNTR);  in intelfbhw_do_blank()
434 	tmp = INREG(DSPABASE);  in intelfbhw_do_blank()
451 	tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;  in intelfbhw_do_blank()
531 	hw->vga0_divisor = INREG(VGA0_DIVISOR);  in intelfbhw_read_hw_state()
532 	hw->vga1_divisor = INREG(VGA1_DIVISOR);  in intelfbhw_read_hw_state()
533 	hw->vga_pd = INREG(VGAPD);  in intelfbhw_read_hw_state()
534 	hw->dpll_a = INREG(DPLL_A);  in intelfbhw_read_hw_state()
535 	hw->dpll_b = INREG(DPLL_B);  in intelfbhw_read_hw_state()
536 	hw->fpa0 = INREG(FPA0);  in intelfbhw_read_hw_state()
537 	hw->fpa1 = INREG(FPA1);  in intelfbhw_read_hw_state()
538 	hw->fpb0 = INREG(FPB0);  in intelfbhw_read_hw_state()
539 	hw->fpb1 = INREG(FPB1);  in intelfbhw_read_hw_state()
547 		hw->palette_a[i] = INREG(PALETTE_A + (i << 2));  in intelfbhw_read_hw_state()
548 		hw->palette_b[i] = INREG(PALETTE_B + (i << 2));  in intelfbhw_read_hw_state()
555 	hw->htotal_a = INREG(HTOTAL_A);  in intelfbhw_read_hw_state()
556 	hw->hblank_a = INREG(HBLANK_A);  in intelfbhw_read_hw_state()
557 	hw->hsync_a = INREG(HSYNC_A);  in intelfbhw_read_hw_state()
558 	hw->vtotal_a = INREG(VTOTAL_A);  in intelfbhw_read_hw_state()
559 	hw->vblank_a = INREG(VBLANK_A);  in intelfbhw_read_hw_state()
560 	hw->vsync_a = INREG(VSYNC_A);  in intelfbhw_read_hw_state()
561 	hw->src_size_a = INREG(SRC_SIZE_A);  in intelfbhw_read_hw_state()
562 	hw->bclrpat_a = INREG(BCLRPAT_A);  in intelfbhw_read_hw_state()
563 	hw->htotal_b = INREG(HTOTAL_B);  in intelfbhw_read_hw_state()
564 	hw->hblank_b = INREG(HBLANK_B);  in intelfbhw_read_hw_state()
565 	hw->hsync_b = INREG(HSYNC_B);  in intelfbhw_read_hw_state()
566 	hw->vtotal_b = INREG(VTOTAL_B);  in intelfbhw_read_hw_state()
567 	hw->vblank_b = INREG(VBLANK_B);  in intelfbhw_read_hw_state()
568 	hw->vsync_b = INREG(VSYNC_B);  in intelfbhw_read_hw_state()
569 	hw->src_size_b = INREG(SRC_SIZE_B);  in intelfbhw_read_hw_state()
570 	hw->bclrpat_b = INREG(BCLRPAT_B);  in intelfbhw_read_hw_state()
575 	hw->adpa = INREG(ADPA);  in intelfbhw_read_hw_state()
576 	hw->dvoa = INREG(DVOA);  in intelfbhw_read_hw_state()
577 	hw->dvob = INREG(DVOB);  in intelfbhw_read_hw_state()
578 	hw->dvoc = INREG(DVOC);  in intelfbhw_read_hw_state()
579 	hw->dvoa_srcdim = INREG(DVOA_SRCDIM);  in intelfbhw_read_hw_state()
580 	hw->dvob_srcdim = INREG(DVOB_SRCDIM);  in intelfbhw_read_hw_state()
581 	hw->dvoc_srcdim = INREG(DVOC_SRCDIM);  in intelfbhw_read_hw_state()
582 	hw->lvds = INREG(LVDS);  in intelfbhw_read_hw_state()
587 	hw->pipe_a_conf = INREG(PIPEACONF);  in intelfbhw_read_hw_state()
588 	hw->pipe_b_conf = INREG(PIPEBCONF);  in intelfbhw_read_hw_state()
589 	hw->disp_arb = INREG(DISPARB);  in intelfbhw_read_hw_state()
594 	hw->cursor_a_control = INREG(CURSOR_A_CONTROL);  in intelfbhw_read_hw_state()
595 	hw->cursor_b_control = INREG(CURSOR_B_CONTROL);  in intelfbhw_read_hw_state()
596 	hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);  in intelfbhw_read_hw_state()
597 	hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);  in intelfbhw_read_hw_state()
603 		hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));  in intelfbhw_read_hw_state()
604 		hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));  in intelfbhw_read_hw_state()
610 	hw->cursor_size = INREG(CURSOR_SIZE);  in intelfbhw_read_hw_state()
615 	hw->disp_a_ctrl = INREG(DSPACNTR);  in intelfbhw_read_hw_state()
616 	hw->disp_b_ctrl = INREG(DSPBCNTR);  in intelfbhw_read_hw_state()
617 	hw->disp_a_base = INREG(DSPABASE);  in intelfbhw_read_hw_state()
618 	hw->disp_b_base = INREG(DSPBBASE);  in intelfbhw_read_hw_state()
619 	hw->disp_a_stride = INREG(DSPASTRIDE);  in intelfbhw_read_hw_state()
620 	hw->disp_b_stride = INREG(DSPBSTRIDE);  in intelfbhw_read_hw_state()
625 	hw->vgacntrl = INREG(VGACNTRL);  in intelfbhw_read_hw_state()
630 	hw->add_id = INREG(ADD_ID);  in intelfbhw_read_hw_state()
636 		hw->swf0x[i] = INREG(SWF00 + (i << 2));  in intelfbhw_read_hw_state()
637 		hw->swf1x[i] = INREG(SWF10 + (i << 2));  in intelfbhw_read_hw_state()
639 			hw->swf3x[i] = INREG(SWF30 + (i << 2));  in intelfbhw_read_hw_state()
643 		hw->fence[i] = INREG(FENCE + (i << 2));  in intelfbhw_read_hw_state()
645 	hw->instpm = INREG(INSTPM);  in intelfbhw_read_hw_state()
646 	hw->mem_mode = INREG(MEM_MODE);  in intelfbhw_read_hw_state()
647 	hw->fw_blc_0 = INREG(FW_BLC_0);  in intelfbhw_read_hw_state()
648 	hw->fw_blc_1 = INREG(FW_BLC_1);  in intelfbhw_read_hw_state()
1296 	tmp = INREG(VGACNTRL);  in intelfbhw_program_mode()
1353 	tmp = INREG(pipe_conf_reg);  in intelfbhw_program_mode()
1359 		tmp_val[count % 3] = INREG(PIPEA_DSL);  in intelfbhw_program_mode()
1365 			tmp = INREG(pipe_conf_reg);  in intelfbhw_program_mode()
1371 	OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);  in intelfbhw_program_mode()
1374 	tmp = INREG(DSPACNTR);  in intelfbhw_program_mode()
1377 	tmp = INREG(DSPBCNTR);  in intelfbhw_program_mode()
1384 	OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);  in intelfbhw_program_mode()
1385 	OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);  in intelfbhw_program_mode()
1386 	OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);  in intelfbhw_program_mode()
1389 	tmp = INREG(ADPA);  in intelfbhw_program_mode()
1398 	tmp = INREG(dpll_reg);  in intelfbhw_program_mode()
1417 	OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);  in intelfbhw_program_mode()
1444 	tmp = INREG(ADPA);  in intelfbhw_program_mode()
1456 		tmp = INREG(DSPACNTR);  in intelfbhw_program_mode()
1472 		tmp = INREG(DSPACNTR);  in intelfbhw_program_mode()
1508 	u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;  in wait_ring()
1516 		dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;  in wait_ring()
1579 	dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;  in refresh_ring()
1580 	dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;  in refresh_ring()
1597 	tmp = INREG(PRI_RING_LENGTH);  in reset_state()
1847 		tmp = INREG(CURSOR_A_CONTROL);  in intelfbhw_cursor_init()
1855 		tmp = INREG(CURSOR_CONTROL);  in intelfbhw_cursor_init()
1879 		tmp = INREG(CURSOR_A_CONTROL);  in intelfbhw_cursor_hide()
1886 		tmp = INREG(CURSOR_CONTROL);  in intelfbhw_cursor_hide()
1908 		tmp = INREG(CURSOR_A_CONTROL);  in intelfbhw_cursor_show()
1915 		tmp = INREG(CURSOR_CONTROL);  in intelfbhw_cursor_show()
2024 	OUTREG(PIPEASTAT, INREG(PIPEASTAT));  in intelfbhw_irq()