Lines Matching +full:invert +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1998-2000 Russell King
77 #define EXT_FUNC_CTL_EXTREGENBL 0x80 /* enable access to 0xbcxxx */
80 #define PCI_BM_CTL_ENABLE 0x01 /* enable bus-master */
81 #define PCI_BM_CTL_BURST 0x02 /* enable burst */
82 #define PCI_BM_CTL_BACK2BACK 0x04 /* enable back to back */
199 #define EXT_CAP_MODE1_8BIT 0x01 /* enable 8bit capture mode */
226 #define EXT_LATCH1_VAFC_EN 0x01 /* enable VAFC */
250 #define EXT_X_START 0xc5 /* ext->screen, 16 bits */
251 #define EXT_X_END 0xc7 /* ext->screen, 16 bits */
252 #define EXT_Y_START 0xc9 /* ext->screen, 16 bits */
253 #define EXT_Y_END 0xcb /* ext->screen, 16 bits */
256 #define EXT_DDA_X_INIT 0xd1 /* ext->screen 16 bits */
257 #define EXT_DDA_X_INC 0xd3 /* ext->screen 16 bits */
258 #define EXT_DDA_Y_INIT 0xd5 /* ext->screen 16 bits */
259 #define EXT_DDA_Y_INC 0xd7 /* ext->screen 16 bits */
264 #define EXT_VID_FMT_YUV422 0x00 /* formats - does this cause conversion? */
285 #define EXT_VID_DISP_CTL1_ENABLE_WINDOW 0x80 /* enable video window */
289 #define EXT_VID_FIFO_CTL1_INTERLEAVE 0x04 /* enable interleaved memory read */
299 #define VFAC_CTL1_CAPTURE 0x01 /* capture enable (only when VSYNC high)*/
300 #define VFAC_CTL1_VFAC_ENABLE 0x02 /* vfac enable */
308 #define VFAC_CTL2_INVERT_VIDDATAVALID 0x01 /* invert video data valid */
309 #define VFAC_CTL2_INVERT_GRAPHREADY 0x02 /* invert graphic ready output sig */
310 #define VFAC_CTL2_INVERT_DATACLK 0x04 /* invert data clock signal */
311 #define VFAC_CTL2_INVERT_HSYNC 0x08 /* invert hsync input */
312 #define VFAC_CTL2_INVERT_VSYNC 0x10 /* invert vsync input */
313 #define VFAC_CTL2_INVERT_FRAME 0x20 /* invert frame odd/even input */
314 #define VFAC_CTL2_INVERT_BLANK 0x40 /* invert blank output */
315 #define VFAC_CTL2_INVERT_OVSYNC 0x80 /* invert other vsync input */
325 #define VFAC_CTL3_CAP_IRQ 0x40 /* enable capture interrupt */
349 * Bus-master
357 #define BM_CONTROL_ENABLE 0x01 /* enable transfer */
358 #define BM_CONTROL_IRQEN 0x02 /* enable IRQ at end of transfer */
360 #define BM_COUNT 0xbc090 /* read-only */
397 #define TV_CTL 0xbe4dc /* reflects a previous register- MVFCLR, MVPCLR etc P241*/
405 * Graphics Co-processor