Lines Matching +full:sense +full:- +full:freq
2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
102 * per-board-type information, used for enumerating and abstracting
103 * chip-specific information
107 * is required at runtime. Maybe separate into an init-only and
108 * a run-time table?
113 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
261 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
374 /*--- Interface used by the world ------------------------------------------*/
378 /*--- Internal routines ----------------------------------------------------*/
407 static void bestclock(long freq, int *nom, int *den, int *div);
422 return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB; in is_laguna()
427 /*--- Open /dev/fbx ---------------------------------------------------------*/
431 switch_monitor(info->par, 1); in cirrusfb_open()
435 /*--- Close /dev/fbx --------------------------------------------------------*/
438 if (--opencount == 0) in cirrusfb_release()
439 switch_monitor(info->par, 0); in cirrusfb_release()
448 static int cirrusfb_check_mclk(struct fb_info *info, long freq) in cirrusfb_check_mclk() argument
450 struct cirrusfb_info *cinfo = info->par; in cirrusfb_check_mclk()
451 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f; in cirrusfb_check_mclk()
455 dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk); in cirrusfb_check_mclk()
461 if (abs(freq - mclk) < 250) { in cirrusfb_check_mclk()
462 dev_dbg(info->device, "Using VCLK = MCLK\n"); in cirrusfb_check_mclk()
464 } else if (abs(freq - (mclk / 2)) < 250) { in cirrusfb_check_mclk()
465 dev_dbg(info->device, "Using VCLK = MCLK/2\n"); in cirrusfb_check_mclk()
475 long freq; in cirrusfb_check_pixclock() local
477 struct cirrusfb_info *cinfo = info->par; in cirrusfb_check_pixclock()
478 unsigned maxclockidx = var->bits_per_pixel >> 3; in cirrusfb_check_pixclock()
481 freq = PICOS2KHZ(var->pixclock); in cirrusfb_check_pixclock()
483 dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq); in cirrusfb_check_pixclock()
485 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx]; in cirrusfb_check_pixclock()
486 cinfo->multiplexing = 0; in cirrusfb_check_pixclock()
490 if (freq > maxclock) { in cirrusfb_check_pixclock()
491 dev_err(info->device, in cirrusfb_check_pixclock()
494 return -EINVAL; in cirrusfb_check_pixclock()
500 if (var->bits_per_pixel == 8) { in cirrusfb_check_pixclock()
501 switch (cinfo->btype) { in cirrusfb_check_pixclock()
505 if (freq > 85500) in cirrusfb_check_pixclock()
506 cinfo->multiplexing = 1; in cirrusfb_check_pixclock()
509 if (freq > 135100) in cirrusfb_check_pixclock()
510 cinfo->multiplexing = 1; in cirrusfb_check_pixclock()
520 cinfo->doubleVCLK = 0; in cirrusfb_check_pixclock()
521 if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ && in cirrusfb_check_pixclock()
522 var->bits_per_pixel == 16) { in cirrusfb_check_pixclock()
523 cinfo->doubleVCLK = 1; in cirrusfb_check_pixclock()
534 unsigned pixels = info->screen_size * 8 / var->bits_per_pixel; in cirrusfb_check_var()
535 struct cirrusfb_info *cinfo = info->par; in cirrusfb_check_var()
537 switch (var->bits_per_pixel) { in cirrusfb_check_var()
539 var->red.offset = 0; in cirrusfb_check_var()
540 var->red.length = 1; in cirrusfb_check_var()
541 var->green = var->red; in cirrusfb_check_var()
542 var->blue = var->red; in cirrusfb_check_var()
546 var->red.offset = 0; in cirrusfb_check_var()
547 var->red.length = 8; in cirrusfb_check_var()
548 var->green = var->red; in cirrusfb_check_var()
549 var->blue = var->red; in cirrusfb_check_var()
553 var->red.offset = 11; in cirrusfb_check_var()
554 var->green.offset = 5; in cirrusfb_check_var()
555 var->blue.offset = 0; in cirrusfb_check_var()
556 var->red.length = 5; in cirrusfb_check_var()
557 var->green.length = 6; in cirrusfb_check_var()
558 var->blue.length = 5; in cirrusfb_check_var()
562 var->red.offset = 16; in cirrusfb_check_var()
563 var->green.offset = 8; in cirrusfb_check_var()
564 var->blue.offset = 0; in cirrusfb_check_var()
565 var->red.length = 8; in cirrusfb_check_var()
566 var->green.length = 8; in cirrusfb_check_var()
567 var->blue.length = 8; in cirrusfb_check_var()
571 dev_dbg(info->device, in cirrusfb_check_var()
572 "Unsupported bpp size: %d\n", var->bits_per_pixel); in cirrusfb_check_var()
573 return -EINVAL; in cirrusfb_check_var()
576 if (var->xres_virtual < var->xres) in cirrusfb_check_var()
577 var->xres_virtual = var->xres; in cirrusfb_check_var()
579 if (var->yres_virtual == -1) { in cirrusfb_check_var()
580 var->yres_virtual = pixels / var->xres_virtual; in cirrusfb_check_var()
582 dev_info(info->device, in cirrusfb_check_var()
584 var->xres_virtual, var->yres_virtual); in cirrusfb_check_var()
586 if (var->yres_virtual < var->yres) in cirrusfb_check_var()
587 var->yres_virtual = var->yres; in cirrusfb_check_var()
589 if (var->xres_virtual * var->yres_virtual > pixels) { in cirrusfb_check_var()
590 dev_err(info->device, "mode %dx%dx%d rejected... " in cirrusfb_check_var()
592 var->xres_virtual, var->yres_virtual, in cirrusfb_check_var()
593 var->bits_per_pixel); in cirrusfb_check_var()
594 return -EINVAL; in cirrusfb_check_var()
598 if (var->xoffset > var->xres_virtual - var->xres) in cirrusfb_check_var()
599 var->xoffset = var->xres_virtual - var->xres - 1; in cirrusfb_check_var()
600 if (var->yoffset > var->yres_virtual - var->yres) in cirrusfb_check_var()
601 var->yoffset = var->yres_virtual - var->yres - 1; in cirrusfb_check_var()
603 var->red.msb_right = in cirrusfb_check_var()
604 var->green.msb_right = in cirrusfb_check_var()
605 var->blue.msb_right = in cirrusfb_check_var()
606 var->transp.offset = in cirrusfb_check_var()
607 var->transp.length = in cirrusfb_check_var()
608 var->transp.msb_right = 0; in cirrusfb_check_var()
610 yres = var->yres; in cirrusfb_check_var()
611 if (var->vmode & FB_VMODE_DOUBLE) in cirrusfb_check_var()
613 else if (var->vmode & FB_VMODE_INTERLACED) in cirrusfb_check_var()
617 dev_err(info->device, "ERROR: VerticalTotal >= 1280; " in cirrusfb_check_var()
619 return -EINVAL; in cirrusfb_check_var()
623 return -EINVAL; in cirrusfb_check_var()
626 var->accel_flags = FB_ACCELF_TEXT; in cirrusfb_check_var()
633 struct cirrusfb_info *cinfo = info->par; in cirrusfb_set_mclk_as_source()
637 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40; in cirrusfb_set_mclk_as_source()
640 dev_dbg(info->device, "Set %s as pixclock source.\n", in cirrusfb_set_mclk_as_source()
643 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1; in cirrusfb_set_mclk_as_source()
647 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e); in cirrusfb_set_mclk_as_source()
649 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f); in cirrusfb_set_mclk_as_source()
659 struct cirrusfb_info *cinfo = info->par; in cirrusfb_set_par_foo()
660 struct fb_var_screeninfo *var = &info->var; in cirrusfb_set_par_foo()
661 u8 __iomem *regbase = cinfo->regbase; in cirrusfb_set_par_foo()
667 long freq; in cirrusfb_set_par_foo() local
671 dev_dbg(info->device, "Requested mode: %dx%dx%d\n", in cirrusfb_set_par_foo()
672 var->xres, var->yres, var->bits_per_pixel); in cirrusfb_set_par_foo()
674 switch (var->bits_per_pixel) { in cirrusfb_set_par_foo()
676 info->fix.line_length = var->xres_virtual / 8; in cirrusfb_set_par_foo()
677 info->fix.visual = FB_VISUAL_MONO10; in cirrusfb_set_par_foo()
681 info->fix.line_length = var->xres_virtual; in cirrusfb_set_par_foo()
682 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; in cirrusfb_set_par_foo()
687 info->fix.line_length = var->xres_virtual * in cirrusfb_set_par_foo()
688 var->bits_per_pixel >> 3; in cirrusfb_set_par_foo()
689 info->fix.visual = FB_VISUAL_TRUECOLOR; in cirrusfb_set_par_foo()
692 info->fix.type = FB_TYPE_PACKED_PIXELS; in cirrusfb_set_par_foo()
696 bi = &cirrusfb_board_info[cinfo->btype]; in cirrusfb_set_par_foo()
698 hsyncstart = var->xres + var->right_margin; in cirrusfb_set_par_foo()
699 hsyncend = hsyncstart + var->hsync_len; in cirrusfb_set_par_foo()
700 htotal = (hsyncend + var->left_margin) / 8; in cirrusfb_set_par_foo()
701 hdispend = var->xres / 8; in cirrusfb_set_par_foo()
705 vdispend = var->yres; in cirrusfb_set_par_foo()
706 vsyncstart = vdispend + var->lower_margin; in cirrusfb_set_par_foo()
707 vsyncend = vsyncstart + var->vsync_len; in cirrusfb_set_par_foo()
708 vtotal = vsyncend + var->upper_margin; in cirrusfb_set_par_foo()
710 if (var->vmode & FB_VMODE_DOUBLE) { in cirrusfb_set_par_foo()
715 } else if (var->vmode & FB_VMODE_INTERLACED) { in cirrusfb_set_par_foo()
729 vdispend -= 1; in cirrusfb_set_par_foo()
730 vsyncstart -= 1; in cirrusfb_set_par_foo()
731 vsyncend -= 1; in cirrusfb_set_par_foo()
732 vtotal -= 2; in cirrusfb_set_par_foo()
734 if (cinfo->multiplexing) { in cirrusfb_set_par_foo()
741 htotal -= 5; in cirrusfb_set_par_foo()
742 hdispend -= 1; in cirrusfb_set_par_foo()
750 dev_dbg(info->device, "CRT0: %d\n", htotal); in cirrusfb_set_par_foo()
753 dev_dbg(info->device, "CRT1: %d\n", hdispend); in cirrusfb_set_par_foo()
756 dev_dbg(info->device, "CRT2: %d\n", var->xres / 8); in cirrusfb_set_par_foo()
757 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8); in cirrusfb_set_par_foo()
760 dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32); in cirrusfb_set_par_foo()
764 dev_dbg(info->device, "CRT4: %d\n", hsyncstart); in cirrusfb_set_par_foo()
770 dev_dbg(info->device, "CRT5: %d\n", tmp); in cirrusfb_set_par_foo()
773 dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff); in cirrusfb_set_par_foo()
791 dev_dbg(info->device, "CRT7: %d\n", tmp); in cirrusfb_set_par_foo()
797 if (var->vmode & FB_VMODE_DOUBLE) in cirrusfb_set_par_foo()
799 dev_dbg(info->device, "CRT9: %d\n", tmp); in cirrusfb_set_par_foo()
802 dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff); in cirrusfb_set_par_foo()
805 dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16); in cirrusfb_set_par_foo()
808 dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff); in cirrusfb_set_par_foo()
811 dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff); in cirrusfb_set_par_foo()
814 dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff); in cirrusfb_set_par_foo()
817 dev_dbg(info->device, "CRT18: 0xff\n"); in cirrusfb_set_par_foo()
821 if (var->vmode & FB_VMODE_INTERLACED) in cirrusfb_set_par_foo()
832 dev_dbg(info->device, "CRT1a: %d\n", tmp); in cirrusfb_set_par_foo()
835 freq = PICOS2KHZ(var->pixclock); in cirrusfb_set_par_foo()
836 if (var->bits_per_pixel == 24) in cirrusfb_set_par_foo()
837 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) in cirrusfb_set_par_foo()
838 freq *= 3; in cirrusfb_set_par_foo()
839 if (cinfo->multiplexing) in cirrusfb_set_par_foo()
840 freq /= 2; in cirrusfb_set_par_foo()
841 if (cinfo->doubleVCLK) in cirrusfb_set_par_foo()
842 freq *= 2; in cirrusfb_set_par_foo()
844 bestclock(freq, &nom, &den, &div); in cirrusfb_set_par_foo()
846 dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n", in cirrusfb_set_par_foo()
847 freq, nom, den, div); in cirrusfb_set_par_foo()
854 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 || in cirrusfb_set_par_foo()
855 cinfo->btype == BT_SD64) { in cirrusfb_set_par_foo()
856 /* if freq is close to mclk or mclk/2 select mclk in cirrusfb_set_par_foo()
859 int divMCLK = cirrusfb_check_mclk(info, freq); in cirrusfb_set_par_foo()
865 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc); in cirrusfb_set_par_foo()
866 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407); in cirrusfb_set_par_foo()
869 if (cinfo->btype == BT_LAGUNAB) { in cirrusfb_set_par_foo()
870 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4); in cirrusfb_set_par_foo()
872 fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4); in cirrusfb_set_par_foo()
875 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc); in cirrusfb_set_par_foo()
876 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407); in cirrusfb_set_par_foo()
877 control = fb_readw(cinfo->laguna_mmio + 0x402); in cirrusfb_set_par_foo()
878 threshold = fb_readw(cinfo->laguna_mmio + 0xea); in cirrusfb_set_par_foo()
888 if ((cinfo->btype == BT_SD64) || in cirrusfb_set_par_foo()
889 (cinfo->btype == BT_ALPINE) || in cirrusfb_set_par_foo()
890 (cinfo->btype == BT_GD5480)) in cirrusfb_set_par_foo()
912 /* mode is used, but I feel better this way.. :-) */ in cirrusfb_set_par_foo()
913 if (var->vmode & FB_VMODE_INTERLACED) in cirrusfb_set_par_foo()
921 if (var->sync & FB_SYNC_HOR_HIGH_ACT) in cirrusfb_set_par_foo()
923 if (var->sync & FB_SYNC_VERT_HIGH_ACT) in cirrusfb_set_par_foo()
939 if (var->bits_per_pixel == 1) { in cirrusfb_set_par_foo()
940 dev_dbg(info->device, "preparing for 1 bit deep display\n"); in cirrusfb_set_par_foo()
944 switch (cinfo->btype) { in cirrusfb_set_par_foo()
953 cinfo->multiplexing ? in cirrusfb_set_par_foo()
954 bi->sr07_1bpp_mux : bi->sr07_1bpp); in cirrusfb_set_par_foo()
964 dev_warn(info->device, "unknown Board\n"); in cirrusfb_set_par_foo()
969 switch (cinfo->btype) { in cirrusfb_set_par_foo()
992 dev_warn(info->device, "unknown Board\n"); in cirrusfb_set_par_foo()
996 /* pixel mask: pass-through for first plane */ in cirrusfb_set_par_foo()
998 if (cinfo->multiplexing) in cirrusfb_set_par_foo()
1016 else if (var->bits_per_pixel == 8) { in cirrusfb_set_par_foo()
1017 dev_dbg(info->device, "preparing for 8 bit deep display\n"); in cirrusfb_set_par_foo()
1018 switch (cinfo->btype) { in cirrusfb_set_par_foo()
1027 cinfo->multiplexing ? in cirrusfb_set_par_foo()
1028 bi->sr07_8bpp_mux : bi->sr07_8bpp); in cirrusfb_set_par_foo()
1039 dev_warn(info->device, "unknown Board\n"); in cirrusfb_set_par_foo()
1043 switch (cinfo->btype) { in cirrusfb_set_par_foo()
1047 /* Fast Page-Mode writes */ in cirrusfb_set_par_foo()
1065 dev_warn(info->device, "unknown board\n"); in cirrusfb_set_par_foo()
1071 if (cinfo->multiplexing) in cirrusfb_set_par_foo()
1085 else if (var->bits_per_pixel == 16) { in cirrusfb_set_par_foo()
1086 dev_dbg(info->device, "preparing for 16 bit deep display\n"); in cirrusfb_set_par_foo()
1087 switch (cinfo->btype) { in cirrusfb_set_par_foo()
1091 /* Fast Page-Mode writes */ in cirrusfb_set_par_foo()
1097 /* Fast Page-Mode writes */ in cirrusfb_set_par_foo()
1106 cinfo->doubleVCLK ? 0xa3 : 0xa7); in cirrusfb_set_par_foo()
1124 dev_warn(info->device, "unknown Board\n"); in cirrusfb_set_par_foo()
1131 WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1); in cirrusfb_set_par_foo()
1144 else if (var->bits_per_pixel == 24) { in cirrusfb_set_par_foo()
1145 dev_dbg(info->device, "preparing for 24 bit deep display\n"); in cirrusfb_set_par_foo()
1146 switch (cinfo->btype) { in cirrusfb_set_par_foo()
1150 /* Fast Page-Mode writes */ in cirrusfb_set_par_foo()
1156 /* Fast Page-Mode writes */ in cirrusfb_set_par_foo()
1182 dev_warn(info->device, "unknown Board\n"); in cirrusfb_set_par_foo()
1188 /* hidden dac reg: 8-8-8 mode (24 or 32) */ in cirrusfb_set_par_foo()
1199 dev_err(info->device, in cirrusfb_set_par_foo()
1201 var->bits_per_pixel); in cirrusfb_set_par_foo()
1203 pitch = info->fix.line_length >> 3; in cirrusfb_set_par_foo()
1209 /* screen start addr #16-18, fastpagemode cycles */ in cirrusfb_set_par_foo()
1213 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) in cirrusfb_set_par_foo()
1232 dev_dbg(info->device, "CRT1e: %d\n", tmp); in cirrusfb_set_par_foo()
1244 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402); in cirrusfb_set_par_foo()
1245 fb_writew(format, cinfo->laguna_mmio + 0xc0); in cirrusfb_set_par_foo()
1246 fb_writew(threshold, cinfo->laguna_mmio + 0xea); in cirrusfb_set_par_foo()
1248 /* finally, turn on everything - turn off "FullBandwidth" bit */ in cirrusfb_set_par_foo()
1253 if (var->vmode & FB_VMODE_CLOCK_HALVE) in cirrusfb_set_par_foo()
1258 dev_dbg(info->device, "CL_SEQR1: %d\n", tmp); in cirrusfb_set_par_foo()
1268 * the registers twice for the settings to take..grr. -dte */
1279 struct cirrusfb_info *cinfo = info->par; in cirrusfb_setcolreg()
1282 return -EINVAL; in cirrusfb_setcolreg()
1284 if (info->fix.visual == FB_VISUAL_TRUECOLOR) { in cirrusfb_setcolreg()
1286 red >>= (16 - info->var.red.length); in cirrusfb_setcolreg()
1287 green >>= (16 - info->var.green.length); in cirrusfb_setcolreg()
1288 blue >>= (16 - info->var.blue.length); in cirrusfb_setcolreg()
1292 v = (red << info->var.red.offset) | in cirrusfb_setcolreg()
1293 (green << info->var.green.offset) | in cirrusfb_setcolreg()
1294 (blue << info->var.blue.offset); in cirrusfb_setcolreg()
1296 cinfo->pseudo_palette[regno] = v; in cirrusfb_setcolreg()
1300 if (info->var.bits_per_pixel == 8) in cirrusfb_setcolreg()
1310 performs display panning - provided hardware permits this
1318 struct cirrusfb_info *cinfo = info->par; in cirrusfb_pan_display()
1322 if (var->vmode & FB_VMODE_YWRAP) in cirrusfb_pan_display()
1323 return -EINVAL; in cirrusfb_pan_display()
1325 xoffset = var->xoffset * info->var.bits_per_pixel / 8; in cirrusfb_pan_display()
1327 base = var->yoffset * info->fix.line_length + xoffset; in cirrusfb_pan_display()
1329 if (info->var.bits_per_pixel == 1) { in cirrusfb_pan_display()
1331 xpix = (unsigned char) (var->xoffset % 8); in cirrusfb_pan_display()
1338 cirrusfb_WaitBLT(cinfo->regbase); in cirrusfb_pan_display()
1341 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff); in cirrusfb_pan_display()
1342 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff); in cirrusfb_pan_display()
1345 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2; in cirrusfb_pan_display()
1354 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp); in cirrusfb_pan_display()
1357 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) { in cirrusfb_pan_display()
1358 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D); in cirrusfb_pan_display()
1363 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp); in cirrusfb_pan_display()
1370 if (info->var.bits_per_pixel == 1) in cirrusfb_pan_display()
1371 vga_wattr(cinfo->regbase, CL_AR33, xpix); in cirrusfb_pan_display()
1381 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking in cirrusfb_blank()
1390 struct cirrusfb_info *cinfo = info->par; in cirrusfb_blank()
1391 int current_mode = cinfo->blank_mode; in cirrusfb_blank()
1393 dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode); in cirrusfb_blank()
1395 if (info->state != FBINFO_STATE_RUNNING || in cirrusfb_blank()
1397 dev_dbg(info->device, "EXIT, returning 0\n"); in cirrusfb_blank()
1410 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf; in cirrusfb_blank()
1411 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val); in cirrusfb_blank()
1428 dev_dbg(info->device, "EXIT, returning 1\n"); in cirrusfb_blank()
1432 vga_wgfx(cinfo->regbase, CL_GRE, val); in cirrusfb_blank()
1434 cinfo->blank_mode = blank_mode; in cirrusfb_blank()
1435 dev_dbg(info->device, "EXIT, returning 0\n"); in cirrusfb_blank()
1447 struct cirrusfb_info *cinfo = info->par; in init_vgachip()
1452 bi = &cirrusfb_board_info[cinfo->btype]; in init_vgachip()
1455 switch (cinfo->btype) { in init_vgachip()
1475 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00); in init_vgachip()
1478 vga_wgfx(cinfo->regbase, CL_GR31, 0x00); in init_vgachip()
1482 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00); in init_vgachip()
1486 vga_wgfx(cinfo->regbase, CL_GR33, 0x00); in init_vgachip()
1495 dev_err(info->device, "Warning: Unknown board type\n"); in init_vgachip()
1500 assert(info->screen_size > 0); in init_vgachip()
1506 if (cinfo->btype != BT_PICASSO4) { in init_vgachip()
1511 if (cinfo->btype != BT_SD64) in init_vgachip()
1515 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03); in init_vgachip()
1518 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21); in init_vgachip()
1520 /* "magic cookie" - doesn't make any sense to me.. */ in init_vgachip()
1521 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */ in init_vgachip()
1523 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12); in init_vgachip()
1525 switch (cinfo->btype) { in init_vgachip()
1527 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98); in init_vgachip()
1535 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8); in init_vgachip()
1539 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f); in init_vgachip()
1540 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0); in init_vgachip()
1545 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff); in init_vgachip()
1547 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00); in init_vgachip()
1549 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a); in init_vgachip()
1551 /* controller-internal base address of video memory */ in init_vgachip()
1552 if (bi->init_sr07) in init_vgachip()
1553 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07); in init_vgachip()
1555 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */ in init_vgachip()
1559 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00); in init_vgachip()
1561 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00); in init_vgachip()
1563 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00); in init_vgachip()
1565 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00); in init_vgachip()
1568 if (cinfo->btype != BT_PICASSO4) { in init_vgachip()
1570 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00); in init_vgachip()
1572 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02); in init_vgachip()
1576 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00); in init_vgachip()
1578 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20); in init_vgachip()
1579 /* Text cursor end: - */ in init_vgachip()
1580 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00); in init_vgachip()
1582 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00); in init_vgachip()
1584 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00); in init_vgachip()
1586 /* Underline Row scanline: - */ in init_vgachip()
1587 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00); in init_vgachip()
1590 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02); in init_vgachip()
1592 /* Set/Reset registers: - */ in init_vgachip()
1593 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00); in init_vgachip()
1594 /* Set/Reset enable: - */ in init_vgachip()
1595 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00); in init_vgachip()
1596 /* Color Compare: - */ in init_vgachip()
1597 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00); in init_vgachip()
1598 /* Data Rotate: - */ in init_vgachip()
1599 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00); in init_vgachip()
1600 /* Read Map Select: - */ in init_vgachip()
1601 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00); in init_vgachip()
1603 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00); in init_vgachip()
1605 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01); in init_vgachip()
1607 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f); in init_vgachip()
1609 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff); in init_vgachip()
1611 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 || in init_vgachip()
1614 vga_wgfx(cinfo->regbase, CL_GRB, 0x20); in init_vgachip()
1619 vga_wgfx(cinfo->regbase, CL_GRB, 0x28); in init_vgachip()
1621 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */ in init_vgachip()
1622 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */ in init_vgachip()
1623 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */ in init_vgachip()
1624 /* Background color byte 1: - */ in init_vgachip()
1625 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */ in init_vgachip()
1626 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */ in init_vgachip()
1629 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00); in init_vgachip()
1630 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01); in init_vgachip()
1631 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02); in init_vgachip()
1632 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03); in init_vgachip()
1633 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04); in init_vgachip()
1634 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05); in init_vgachip()
1635 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06); in init_vgachip()
1636 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07); in init_vgachip()
1637 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08); in init_vgachip()
1638 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09); in init_vgachip()
1639 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a); in init_vgachip()
1640 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b); in init_vgachip()
1641 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c); in init_vgachip()
1642 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d); in init_vgachip()
1643 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e); in init_vgachip()
1644 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f); in init_vgachip()
1647 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01); in init_vgachip()
1649 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00); in init_vgachip()
1651 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f); in init_vgachip()
1652 /* Color Select: - */ in init_vgachip()
1653 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00); in init_vgachip()
1658 vga_wgfx(cinfo->regbase, CL_GR31, 0x04); in init_vgachip()
1659 /* - " - : "end-of-reset" */ in init_vgachip()
1660 vga_wgfx(cinfo->regbase, CL_GR31, 0x00); in init_vgachip()
1663 WHDR(cinfo, 0); /* Hidden DAC register: - */ in init_vgachip()
1672 if (cinfo->btype == BT_PICASSO4) in switch_monitor()
1674 if (cinfo->btype == BT_ALPINE) in switch_monitor()
1676 if (cinfo->btype == BT_GD5480) in switch_monitor()
1678 if (cinfo->btype == BT_PICASSO) { in switch_monitor()
1684 switch (cinfo->btype) { in switch_monitor()
1686 WSFR(cinfo, cinfo->SFR | 0x21); in switch_monitor()
1689 WSFR(cinfo, cinfo->SFR | 0x28); in switch_monitor()
1697 switch (cinfo->btype) { in switch_monitor()
1699 WSFR(cinfo, cinfo->SFR & 0xde); in switch_monitor()
1702 WSFR(cinfo, cinfo->SFR & 0xd7); in switch_monitor()
1715 /* Linux 2.6-style accelerated functions */
1720 struct cirrusfb_info *cinfo = info->par; in cirrusfb_sync()
1723 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03) in cirrusfb_sync()
1734 struct cirrusfb_info *cinfo = info->par; in cirrusfb_fillrect()
1735 int m = info->var.bits_per_pixel; in cirrusfb_fillrect()
1736 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ? in cirrusfb_fillrect()
1737 cinfo->pseudo_palette[region->color] : region->color; in cirrusfb_fillrect()
1739 if (info->state != FBINFO_STATE_RUNNING) in cirrusfb_fillrect()
1741 if (info->flags & FBINFO_HWACCEL_DISABLED) { in cirrusfb_fillrect()
1746 vxres = info->var.xres_virtual; in cirrusfb_fillrect()
1747 vyres = info->var.yres_virtual; in cirrusfb_fillrect()
1756 modded.width = vxres - modded.dx; in cirrusfb_fillrect()
1758 modded.height = vyres - modded.dy; in cirrusfb_fillrect()
1760 cirrusfb_RectFill(cinfo->regbase, in cirrusfb_fillrect()
1761 info->var.bits_per_pixel, in cirrusfb_fillrect()
1762 (region->dx * m) / 8, region->dy, in cirrusfb_fillrect()
1763 (region->width * m) / 8, region->height, in cirrusfb_fillrect()
1765 info->fix.line_length, 0x40); in cirrusfb_fillrect()
1773 struct cirrusfb_info *cinfo = info->par; in cirrusfb_copyarea()
1774 int m = info->var.bits_per_pixel; in cirrusfb_copyarea()
1776 if (info->state != FBINFO_STATE_RUNNING) in cirrusfb_copyarea()
1778 if (info->flags & FBINFO_HWACCEL_DISABLED) { in cirrusfb_copyarea()
1783 vxres = info->var.xres_virtual; in cirrusfb_copyarea()
1784 vyres = info->var.yres_virtual; in cirrusfb_copyarea()
1793 modded.width = vxres - modded.sx; in cirrusfb_copyarea()
1795 modded.width = vxres - modded.dx; in cirrusfb_copyarea()
1797 modded.height = vyres - modded.sy; in cirrusfb_copyarea()
1799 modded.height = vyres - modded.dy; in cirrusfb_copyarea()
1801 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel, in cirrusfb_copyarea()
1802 (area->sx * m) / 8, area->sy, in cirrusfb_copyarea()
1803 (area->dx * m) / 8, area->dy, in cirrusfb_copyarea()
1804 (area->width * m) / 8, area->height, in cirrusfb_copyarea()
1805 info->fix.line_length); in cirrusfb_copyarea()
1812 struct cirrusfb_info *cinfo = info->par; in cirrusfb_imageblit()
1813 unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4; in cirrusfb_imageblit()
1815 if (info->state != FBINFO_STATE_RUNNING) in cirrusfb_imageblit()
1818 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) in cirrusfb_imageblit()
1820 else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) && in cirrusfb_imageblit()
1824 unsigned size = ((image->width + 7) >> 3) * image->height; in cirrusfb_imageblit()
1825 int m = info->var.bits_per_pixel; in cirrusfb_imageblit()
1828 if (info->var.bits_per_pixel == 8) { in cirrusfb_imageblit()
1829 fg = image->fg_color; in cirrusfb_imageblit()
1830 bg = image->bg_color; in cirrusfb_imageblit()
1832 fg = ((u32 *)(info->pseudo_palette))[image->fg_color]; in cirrusfb_imageblit()
1833 bg = ((u32 *)(info->pseudo_palette))[image->bg_color]; in cirrusfb_imageblit()
1835 if (info->var.bits_per_pixel == 24) { in cirrusfb_imageblit()
1837 cirrusfb_RectFill(cinfo->regbase, in cirrusfb_imageblit()
1838 info->var.bits_per_pixel, in cirrusfb_imageblit()
1839 (image->dx * m) / 8, image->dy, in cirrusfb_imageblit()
1840 (image->width * m) / 8, in cirrusfb_imageblit()
1841 image->height, in cirrusfb_imageblit()
1843 info->fix.line_length, 0x40); in cirrusfb_imageblit()
1845 cirrusfb_RectFill(cinfo->regbase, in cirrusfb_imageblit()
1846 info->var.bits_per_pixel, in cirrusfb_imageblit()
1847 (image->dx * m) / 8, image->dy, in cirrusfb_imageblit()
1848 (image->width * m) / 8, image->height, in cirrusfb_imageblit()
1850 info->fix.line_length, op); in cirrusfb_imageblit()
1851 memcpy(info->screen_base, image->data, size); in cirrusfb_imageblit()
1866 struct cirrusfb_info *cinfo = info->par; in cirrusfb_get_memsize()
1881 /* 64-bit DRAM data bus width; assume 2MB. in cirrusfb_get_memsize()
1888 dev_warn(info->device, "Unknown memory size!\n"); in cirrusfb_get_memsize()
1894 if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0) in cirrusfb_get_memsize()
1912 /* This is a best-guess for now */ in get_pci_addrs()
1927 struct pci_dev *pdev = to_pci_dev(info->device); in cirrusfb_pci_unmap()
1928 struct cirrusfb_info *cinfo = info->par; in cirrusfb_pci_unmap()
1930 if (cinfo->laguna_mmio == NULL) in cirrusfb_pci_unmap()
1931 iounmap(cinfo->laguna_mmio); in cirrusfb_pci_unmap()
1932 iounmap(info->screen_base); in cirrusfb_pci_unmap()
1945 struct cirrusfb_info *cinfo = info->par; in cirrusfb_zorro_unmap()
1946 struct zorro_dev *zdev = to_zorro_dev(info->device); in cirrusfb_zorro_unmap()
1948 if (info->fix.smem_start > 16 * MB_) in cirrusfb_zorro_unmap()
1949 iounmap(info->screen_base); in cirrusfb_zorro_unmap()
1950 if (info->fix.mmio_start > 16 * MB_) in cirrusfb_zorro_unmap()
1951 iounmap(cinfo->regbase); in cirrusfb_zorro_unmap()
1975 struct cirrusfb_info *cinfo = info->par; in cirrusfb_set_fbinfo()
1976 struct fb_var_screeninfo *var = &info->var; in cirrusfb_set_fbinfo()
1978 info->pseudo_palette = cinfo->pseudo_palette; in cirrusfb_set_fbinfo()
1979 info->flags = FBINFO_DEFAULT in cirrusfb_set_fbinfo()
1986 info->flags |= FBINFO_HWACCEL_DISABLED; in cirrusfb_set_fbinfo()
1987 info->fix.accel = FB_ACCEL_NONE; in cirrusfb_set_fbinfo()
1989 info->fix.accel = FB_ACCEL_CIRRUS_ALPINE; in cirrusfb_set_fbinfo()
1991 info->fbops = &cirrusfb_ops; in cirrusfb_set_fbinfo()
1993 if (cinfo->btype == BT_GD5480) { in cirrusfb_set_fbinfo()
1994 if (var->bits_per_pixel == 16) in cirrusfb_set_fbinfo()
1995 info->screen_base += 1 * MB_; in cirrusfb_set_fbinfo()
1996 if (var->bits_per_pixel == 32) in cirrusfb_set_fbinfo()
1997 info->screen_base += 2 * MB_; in cirrusfb_set_fbinfo()
2001 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name, in cirrusfb_set_fbinfo()
2002 sizeof(info->fix.id)); in cirrusfb_set_fbinfo()
2006 info->fix.smem_len = info->screen_size; in cirrusfb_set_fbinfo()
2007 if (var->bits_per_pixel == 1) in cirrusfb_set_fbinfo()
2008 info->fix.smem_len /= 4; in cirrusfb_set_fbinfo()
2009 info->fix.type_aux = 0; in cirrusfb_set_fbinfo()
2010 info->fix.xpanstep = 1; in cirrusfb_set_fbinfo()
2011 info->fix.ypanstep = 1; in cirrusfb_set_fbinfo()
2012 info->fix.ywrapstep = 0; in cirrusfb_set_fbinfo()
2015 info->fix.mmio_len = 0; in cirrusfb_set_fbinfo()
2017 fb_alloc_cmap(&info->cmap, 256, 0); in cirrusfb_set_fbinfo()
2024 struct cirrusfb_info *cinfo = info->par; in cirrusfb_register()
2028 assert(cinfo->btype != BT_NONE); in cirrusfb_register()
2033 dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base); in cirrusfb_register()
2035 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8); in cirrusfb_register()
2037 dev_dbg(info->device, "wrong initial video mode\n"); in cirrusfb_register()
2038 err = -EINVAL; in cirrusfb_register()
2042 info->var.activate = FB_ACTIVATE_NOW; in cirrusfb_register()
2044 err = cirrusfb_check_var(&info->var, info); in cirrusfb_register()
2047 dev_dbg(info->device, in cirrusfb_register()
2054 dev_err(info->device, in cirrusfb_register()
2062 fb_dealloc_cmap(&info->cmap); in cirrusfb_register()
2068 struct cirrusfb_info *cinfo = info->par; in cirrusfb_cleanup()
2072 fb_dealloc_cmap(&info->cmap); in cirrusfb_cleanup()
2073 dev_dbg(info->device, "Framebuffer unregistered\n"); in cirrusfb_cleanup()
2074 cinfo->unmap(info); in cirrusfb_cleanup()
2093 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev); in cirrusfb_pci_register()
2095 ret = -ENOMEM; in cirrusfb_pci_register()
2099 cinfo = info->par; in cirrusfb_pci_register()
2100 cinfo->btype = (enum cirrus_board) ent->driver_data; in cirrusfb_pci_register()
2102 dev_dbg(info->device, in cirrusfb_pci_register()
2104 (unsigned long long)pdev->resource[0].start, cinfo->btype); in cirrusfb_pci_register()
2105 dev_dbg(info->device, " base address 1 is 0x%Lx\n", in cirrusfb_pci_register()
2106 (unsigned long long)pdev->resource[1].start); in cirrusfb_pci_register()
2108 dev_dbg(info->device, in cirrusfb_pci_register()
2110 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start); in cirrusfb_pci_register()
2112 cinfo->regbase = NULL; in cirrusfb_pci_register()
2113 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000); in cirrusfb_pci_register()
2115 dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n", in cirrusfb_pci_register()
2116 board_addr, info->fix.mmio_start); in cirrusfb_pci_register()
2118 board_size = (cinfo->btype == BT_GD5480) ? in cirrusfb_pci_register()
2119 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase); in cirrusfb_pci_register()
2123 dev_err(info->device, "cannot reserve region 0x%lx, abort\n", in cirrusfb_pci_register()
2129 dev_err(info->device, "cannot reserve region 0x%lx, abort\n", in cirrusfb_pci_register()
2131 ret = -EBUSY; in cirrusfb_pci_register()
2138 info->screen_base = ioremap(board_addr, board_size); in cirrusfb_pci_register()
2139 if (!info->screen_base) { in cirrusfb_pci_register()
2140 ret = -EIO; in cirrusfb_pci_register()
2144 info->fix.smem_start = board_addr; in cirrusfb_pci_register()
2145 info->screen_size = board_size; in cirrusfb_pci_register()
2146 cinfo->unmap = cirrusfb_pci_unmap; in cirrusfb_pci_register()
2148 dev_info(info->device, in cirrusfb_pci_register()
2150 info->screen_size >> 10, board_addr); in cirrusfb_pci_register()
2157 iounmap(info->screen_base); in cirrusfb_pci_register()
2167 if (cinfo->laguna_mmio != NULL) in cirrusfb_pci_register()
2168 iounmap(cinfo->laguna_mmio); in cirrusfb_pci_register()
2206 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev); in cirrusfb_zorro_register()
2208 return -ENOMEM; in cirrusfb_zorro_register()
2210 zcl = (const struct zorrocl *)ent->driver_data; in cirrusfb_zorro_register()
2211 btype = zcl->type; in cirrusfb_zorro_register()
2212 regbase = zorro_resource_start(z) + zcl->regoffset; in cirrusfb_zorro_register()
2213 ramsize = zcl->ramsize; in cirrusfb_zorro_register()
2215 rambase = zorro_resource_start(z) + zcl->ramoffset; in cirrusfb_zorro_register()
2218 rambase += zcl->ramoffset; in cirrusfb_zorro_register()
2221 struct zorro_dev *ram = zorro_find_device(zcl->ramid, NULL); in cirrusfb_zorro_register()
2223 dev_err(info->device, "No video RAM found\n"); in cirrusfb_zorro_register()
2224 error = -ENODEV; in cirrusfb_zorro_register()
2229 if (zcl->ramid2 && in cirrusfb_zorro_register()
2230 (ram = zorro_find_device(zcl->ramid2, NULL))) { in cirrusfb_zorro_register()
2232 dev_warn(info->device, in cirrusfb_zorro_register()
2233 "Skipping non-contiguous RAM at %pR\n", in cirrusfb_zorro_register()
2234 &ram->resource); in cirrusfb_zorro_register()
2241 dev_info(info->device, in cirrusfb_zorro_register()
2247 dev_err(info->device, "Cannot reserve %pR\n", &z->resource); in cirrusfb_zorro_register()
2248 error = -EBUSY; in cirrusfb_zorro_register()
2252 cinfo = info->par; in cirrusfb_zorro_register()
2253 cinfo->btype = btype; in cirrusfb_zorro_register()
2255 info->fix.mmio_start = regbase; in cirrusfb_zorro_register()
2256 cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024) in cirrusfb_zorro_register()
2258 if (!cinfo->regbase) { in cirrusfb_zorro_register()
2259 dev_err(info->device, "Cannot map registers\n"); in cirrusfb_zorro_register()
2260 error = -EIO; in cirrusfb_zorro_register()
2264 info->fix.smem_start = rambase; in cirrusfb_zorro_register()
2265 info->screen_size = ramsize; in cirrusfb_zorro_register()
2266 info->screen_base = rambase > 16 * MB_ ? ioremap(rambase, ramsize) in cirrusfb_zorro_register()
2268 if (!info->screen_base) { in cirrusfb_zorro_register()
2269 dev_err(info->device, "Cannot map video RAM\n"); in cirrusfb_zorro_register()
2270 error = -EIO; in cirrusfb_zorro_register()
2274 cinfo->unmap = cirrusfb_zorro_unmap; in cirrusfb_zorro_register()
2276 dev_info(info->device, in cirrusfb_zorro_register()
2282 vga_wseq(cinfo->regbase, CL_SEQR1F, in cirrusfb_zorro_register()
2287 dev_err(info->device, "Failed to register device, error %d\n", in cirrusfb_zorro_register()
2297 iounmap(info->screen_base); in cirrusfb_zorro_register()
2301 iounmap(cinfo->regbase); in cirrusfb_zorro_register()
2364 return -ENODEV; in cirrusfb_init()
2390 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
2399 /* about the following functions - I have used the same names for the */
2401 /* they just made sense for this purpose. Apart from that, I wrote */
2405 /*** WGen() - write into one of the external/general registers ***/
2411 if (cinfo->btype == BT_PICASSO) { in WGen()
2419 vga_w(cinfo->regbase, regofs + regnum, val); in WGen()
2422 /*** RGen() - read out one of the external/general registers ***/
2427 if (cinfo->btype == BT_PICASSO) { in RGen()
2435 return vga_r(cinfo->regbase, regofs + regnum); in RGen()
2438 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2443 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) { in AttrOn()
2446 vga_w(cinfo->regbase, VGA_ATT_IW, in AttrOn()
2447 vga_r(cinfo->regbase, VGA_ATT_R)); in AttrOn()
2450 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */ in AttrOn()
2451 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33); in AttrOn()
2454 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00); in AttrOn()
2457 /*** WHDR() - write into the Hidden DAC register ***/
2469 if (cinfo->btype == BT_PICASSO) { in WHDR()
2492 if (cinfo->btype == BT_PICASSO) { in WHDR()
2504 /*** WSFR() - write to the "special function register" (SFR) ***/
2508 assert(cinfo->regbase != NULL); in WSFR()
2509 cinfo->SFR = val; in WSFR()
2510 z_writeb(val, cinfo->regbase + 0x8000); in WSFR()
2520 assert(cinfo->regbase != NULL); in WSFR2()
2521 cinfo->SFR = val; in WSFR2()
2522 z_writeb(val, cinfo->regbase + 0x9000); in WSFR2()
2526 /*** WClut - set CLUT entry (range: 0..63) ***/
2533 vga_w(cinfo->regbase, VGA_PEL_IW, regnum); in WClut()
2535 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 || in WClut()
2536 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 || in WClut()
2537 cinfo->btype == BT_SD64 || is_laguna(cinfo)) { in WClut()
2539 if (cinfo->btype == BT_PICASSO) in WClut()
2541 vga_w(cinfo->regbase, data, red); in WClut()
2542 vga_w(cinfo->regbase, data, green); in WClut()
2543 vga_w(cinfo->regbase, data, blue); in WClut()
2545 vga_w(cinfo->regbase, data, blue); in WClut()
2546 vga_w(cinfo->regbase, data, green); in WClut()
2547 vga_w(cinfo->regbase, data, red); in WClut()
2552 /*** RClut - read CLUT entry (range 0..63) ***/
2558 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2560 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2561 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2562 if (cinfo->btype == BT_PICASSO)
2564 *red = vga_r(cinfo->regbase, data);
2565 *green = vga_r(cinfo->regbase, data);
2566 *blue = vga_r(cinfo->regbase, data);
2568 *blue = vga_r(cinfo->regbase, data);
2569 *green = vga_r(cinfo->regbase, data);
2570 *red = vga_r(cinfo->regbase, data);
2610 /* BLT width: actual number of pixels - 1 */ in cirrusfb_set_blitter()
2616 /* BLT height: actual number of lines -1 */ in cirrusfb_set_blitter()
2660 u_short nwidth = width - 1; in cirrusfb_BitBLT()
2661 u_short nheight = height - 1; in cirrusfb_BitBLT()
2729 cirrusfb_set_blitter(regbase, width - 1, height - 1, in cirrusfb_RectFill()
2734 * bestclock() - determine closest possible clock lower(?) than the
2737 static void bestclock(long freq, int *nom, int *den, int *div) in bestclock() argument
2750 if (freq < 8000) in bestclock()
2751 freq = 8000; in bestclock()
2753 diff = freq; in bestclock()
2758 d = (14318 * n) / freq; in bestclock()
2767 h = h > freq ? h - freq : freq - h; in bestclock()
2782 h = h > freq ? h - freq : freq - h; in bestclock()
2793 /* -------------------------------------------------------------------------
2797 * -------------------------------------------------------------------------
2809 * old-style I/O ports are queried for information, otherwise MMIO is
2841 dev_dbg(info->device, "%8s = 0x%02X\n", name, val); in cirrusfb_dbg_print_regs()
2855 * old-style I/O ports are queried for information, otherwise MMIO is
2861 dev_dbg(info->device, "VGA CRTC register dump:\n"); in cirrusfb_dbg_reg_dump()
2913 dev_dbg(info->device, "\n"); in cirrusfb_dbg_reg_dump()
2915 dev_dbg(info->device, "VGA SEQ register dump:\n"); in cirrusfb_dbg_reg_dump()
2946 dev_dbg(info->device, "\n"); in cirrusfb_dbg_reg_dump()