Lines Matching refs:pllSPLL_CNTL
662 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL); in radeon_pm_save_regs()
1468 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_all_ppls_off()
1469 OUTPLL(pllSPLL_CNTL, tmp | 0x3); in radeon_pm_all_ppls_off()
1483 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1484 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_start_mclk_sclk()
1495 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1496 OUTPLL(pllSPLL_CNTL, tmp & ~1); in radeon_pm_start_mclk_sclk()
1497 (void)INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1502 tmp = INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1503 OUTPLL(pllSPLL_CNTL, tmp & ~0x2); in radeon_pm_start_mclk_sclk()
1504 (void)INPLL(pllSPLL_CNTL); in radeon_pm_start_mclk_sclk()
1658 OUTREG8(CLOCK_CNTL_INDEX, pllSPLL_CNTL + PLL_WR_EN); in radeon_pm_restore_pixel_pll()
1863 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M10()
2095 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03); in radeon_reinitialize_M9P()