Lines Matching +full:ati +full:- +full:base
4 * framebuffer driver for ATI Radeon chipset video boards
11 * Special thanks to ATI DevRel team for their hardware donations.
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
262 static int default_dynclk = -2;
282 if (rinfo->no_schedule || oops_in_progress) in _radeon_msleep()
290 /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */ in radeon_pll_errata_after_index_slow()
297 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) { in radeon_pll_errata_after_data_slow()
301 if (rinfo->errata & CHIP_ERRATA_R300_CG) { in radeon_pll_errata_after_data_slow()
316 spin_lock_irqsave(&rinfo->reg_lock, flags); in _OUTREGP()
321 spin_unlock_irqrestore(&rinfo->reg_lock, flags); in _OUTREGP()
409 if (!rinfo->bios_seg) in radeon_unmap_ROM()
411 pci_unmap_rom(dev, rinfo->bios_seg); in radeon_unmap_ROM()
426 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */ in radeon_map_ROM()
437 pci_name(rinfo->pdev)); in radeon_map_ROM()
438 return -ENOMEM; in radeon_map_ROM()
441 rinfo->bios_seg = rom; in radeon_map_ROM()
447 pci_name(rinfo->pdev), BIOS_IN16(0)); in radeon_map_ROM()
459 * relative start of ROM, but so far, I never found a dual-image ATI card in radeon_map_ROM()
479 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr)); in radeon_map_ROM()
491 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n"); in radeon_map_ROM()
499 rinfo->fp_bios_start = BIOS_IN16(0x48); in radeon_map_ROM()
503 rinfo->bios_seg = NULL; in radeon_map_ROM()
505 return -ENXIO; in radeon_map_ROM()
522 return -ENOMEM; in radeon_find_mem_vbios()
529 return -ENXIO; in radeon_find_mem_vbios()
532 rinfo->bios_seg = rom_base; in radeon_find_mem_vbios()
533 rinfo->fp_bios_start = BIOS_IN16(0x48); in radeon_find_mem_vbios()
542 * tree. Hopefully, ATI OF driver is kind enough to fill these
546 struct device_node *dp = rinfo->of_node; in radeon_read_xtal_OF()
550 return -ENODEV; in radeon_read_xtal_OF()
554 return -EINVAL; in radeon_read_xtal_OF()
557 rinfo->pll.ref_clk = (*val) / 10; in radeon_read_xtal_OF()
561 rinfo->pll.sclk = (*val) / 10; in radeon_read_xtal_OF()
565 rinfo->pll.mclk = (*val) / 10; in radeon_read_xtal_OF()
587 * here, so... --BenH in radeon_probe_pll_params()
615 return -1; in radeon_probe_pll_params()
684 return -1; in radeon_probe_pll_params()
697 rinfo->pll.ref_clk = xtal; in radeon_probe_pll_params()
698 rinfo->pll.ref_div = ref_div; in radeon_probe_pll_params()
699 rinfo->pll.sclk = sclk; in radeon_probe_pll_params()
700 rinfo->pll.mclk = mclk; in radeon_probe_pll_params()
715 switch (rinfo->chipset) { in radeon_get_pllinfo()
718 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
719 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
720 rinfo->pll.mclk = 23000; in radeon_get_pllinfo()
721 rinfo->pll.sclk = 23000; in radeon_get_pllinfo()
722 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
729 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
730 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
731 rinfo->pll.mclk = 27500; in radeon_get_pllinfo()
732 rinfo->pll.sclk = 27500; in radeon_get_pllinfo()
733 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
739 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
740 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
741 rinfo->pll.mclk = 25000; in radeon_get_pllinfo()
742 rinfo->pll.sclk = 25000; in radeon_get_pllinfo()
743 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
749 rinfo->pll.ppll_max = 40000; in radeon_get_pllinfo()
750 rinfo->pll.ppll_min = 20000; in radeon_get_pllinfo()
751 rinfo->pll.mclk = 27000; in radeon_get_pllinfo()
752 rinfo->pll.sclk = 27000; in radeon_get_pllinfo()
753 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
760 rinfo->pll.ppll_max = 35000; in radeon_get_pllinfo()
761 rinfo->pll.ppll_min = 12000; in radeon_get_pllinfo()
762 rinfo->pll.mclk = 16600; in radeon_get_pllinfo()
763 rinfo->pll.sclk = 16600; in radeon_get_pllinfo()
764 rinfo->pll.ref_clk = 2700; in radeon_get_pllinfo()
767 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in radeon_get_pllinfo()
784 if (!force_measure_pll && rinfo->bios_seg) { in radeon_get_pllinfo()
785 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); in radeon_get_pllinfo()
787 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); in radeon_get_pllinfo()
788 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a); in radeon_get_pllinfo()
789 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); in radeon_get_pllinfo()
790 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); in radeon_get_pllinfo()
791 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); in radeon_get_pllinfo()
792 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); in radeon_get_pllinfo()
808 * Fall back to already-set defaults... in radeon_get_pllinfo()
818 if (rinfo->pll.mclk == 0) in radeon_get_pllinfo()
819 rinfo->pll.mclk = 20000; in radeon_get_pllinfo()
820 if (rinfo->pll.sclk == 0) in radeon_get_pllinfo()
821 rinfo->pll.sclk = 20000; in radeon_get_pllinfo()
824 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100, in radeon_get_pllinfo()
825 rinfo->pll.ref_div, in radeon_get_pllinfo()
826 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100, in radeon_get_pllinfo()
827 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100); in radeon_get_pllinfo()
828 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max); in radeon_get_pllinfo()
833 struct radeonfb_info *rinfo = info->par; in radeonfb_check_var()
839 return -EINVAL; in radeonfb_check_var()
852 return -EINVAL; in radeonfb_check_var()
903 var->xres, var->yres, var->bits_per_pixel); in radeonfb_check_var()
904 return -EINVAL; in radeonfb_check_var()
916 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) { in radeonfb_check_var()
924 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram) in radeonfb_check_var()
925 return -EINVAL; in radeonfb_check_var()
930 if (v.xoffset > v.xres_virtual - v.xres) in radeonfb_check_var()
931 v.xoffset = v.xres_virtual - v.xres - 1; in radeonfb_check_var()
933 if (v.yoffset > v.yres_virtual - v.yres) in radeonfb_check_var()
934 v.yoffset = v.yres_virtual - v.yres - 1; in radeonfb_check_var()
949 struct radeonfb_info *rinfo = info->par; in radeonfb_pan_display()
951 if ((var->xoffset + info->var.xres > info->var.xres_virtual) in radeonfb_pan_display()
952 || (var->yoffset + info->var.yres > info->var.yres_virtual)) in radeonfb_pan_display()
953 return -EINVAL; in radeonfb_pan_display()
955 if (rinfo->asleep) in radeonfb_pan_display()
959 OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length + in radeonfb_pan_display()
960 var->xoffset * info->var.bits_per_pixel / 8) & ~7); in radeonfb_pan_display()
968 struct radeonfb_info *rinfo = info->par; in radeonfb_ioctl()
975 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's in radeonfb_ioctl()
980 if (!rinfo->is_mobility) in radeonfb_ioctl()
981 return -EINVAL; in radeonfb_ioctl()
1017 if (!rinfo->is_mobility) in radeonfb_ioctl()
1018 return -EINVAL; in radeonfb_ioctl()
1030 return -EINVAL; in radeonfb_ioctl()
1033 return -EINVAL; in radeonfb_ioctl()
1043 if (rinfo->lock_blank) in radeon_screen_blank()
1072 switch (rinfo->mon1_type) { in radeon_screen_blank()
1084 del_timer_sync(&rinfo->lvds_timer); in radeon_screen_blank()
1088 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl in radeon_screen_blank()
1095 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; in radeon_screen_blank()
1096 rinfo->init_state.lvds_gen_cntl |= in radeon_screen_blank()
1099 radeon_msleep(rinfo->panel_info.pwr_delay); in radeon_screen_blank()
1103 rinfo->pending_lvds_gen_cntl = target_val; in radeon_screen_blank()
1104 mod_timer(&rinfo->lvds_timer, in radeon_screen_blank()
1106 msecs_to_jiffies(rinfo->panel_info.pwr_delay)); in radeon_screen_blank()
1113 /* We don't do a full switch-off on a simple mode switch */ in radeon_screen_blank()
1121 if (rinfo->is_mobility || rinfo->is_IGP) in radeon_screen_blank()
1129 rinfo->pending_lvds_gen_cntl = val; in radeon_screen_blank()
1130 mod_timer(&rinfo->lvds_timer, in radeon_screen_blank()
1132 msecs_to_jiffies(rinfo->panel_info.pwr_delay)); in radeon_screen_blank()
1133 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK; in radeon_screen_blank()
1134 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK; in radeon_screen_blank()
1135 if (rinfo->is_mobility || rinfo->is_IGP) in radeon_screen_blank()
1150 struct radeonfb_info *rinfo = info->par; in radeonfb_blank()
1152 if (rinfo->asleep) in radeonfb_blank()
1167 return -EINVAL; in radeon_setcolreg()
1172 rinfo->palette[regno].red = red; in radeon_setcolreg()
1173 rinfo->palette[regno].green = green; in radeon_setcolreg()
1174 rinfo->palette[regno].blue = blue; in radeon_setcolreg()
1179 if (!rinfo->asleep) { in radeon_setcolreg()
1182 if (rinfo->bpp == 16) { in radeon_setcolreg()
1185 if (rinfo->depth == 16 && regno > 63) in radeon_setcolreg()
1186 return -EINVAL; in radeon_setcolreg()
1187 if (rinfo->depth == 15 && regno > 31) in radeon_setcolreg()
1188 return -EINVAL; in radeon_setcolreg()
1193 if (rinfo->depth == 16) { in radeon_setcolreg()
1196 (rinfo->palette[regno>>1].red << 16) | in radeon_setcolreg()
1198 (rinfo->palette[regno>>1].blue)); in radeon_setcolreg()
1199 green = rinfo->palette[regno<<1].green; in radeon_setcolreg()
1203 if (rinfo->depth != 16 || regno < 32) { in radeon_setcolreg()
1210 u32 *pal = rinfo->info->pseudo_palette; in radeon_setcolreg()
1211 switch (rinfo->depth) { in radeon_setcolreg()
1234 struct radeonfb_info *rinfo = info->par; in radeonfb_setcolreg()
1238 if (!rinfo->asleep) { in radeonfb_setcolreg()
1239 if (rinfo->is_mobility) { in radeonfb_setcolreg()
1246 if (rinfo->has_CRTC2) { in radeonfb_setcolreg()
1255 if (!rinfo->asleep && rinfo->is_mobility) in radeonfb_setcolreg()
1263 struct radeonfb_info *rinfo = info->par; in radeonfb_setcmap()
1268 if (!rinfo->asleep) { in radeonfb_setcmap()
1269 if (rinfo->is_mobility) { in radeonfb_setcmap()
1276 if (rinfo->has_CRTC2) { in radeonfb_setcmap()
1283 red = cmap->red; in radeonfb_setcmap()
1284 green = cmap->green; in radeonfb_setcmap()
1285 blue = cmap->blue; in radeonfb_setcmap()
1286 transp = cmap->transp; in radeonfb_setcmap()
1287 start = cmap->start; in radeonfb_setcmap()
1289 for (i = 0; i < cmap->len; i++) { in radeonfb_setcmap()
1303 if (!rinfo->asleep && rinfo->is_mobility) in radeonfb_setcmap()
1313 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL); in radeon_save_state()
1314 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL); in radeon_save_state()
1315 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL); in radeon_save_state()
1316 save->dac_cntl = INREG(DAC_CNTL); in radeon_save_state()
1317 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP); in radeon_save_state()
1318 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID); in radeon_save_state()
1319 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP); in radeon_save_state()
1320 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID); in radeon_save_state()
1321 save->crtc_pitch = INREG(CRTC_PITCH); in radeon_save_state()
1322 save->surface_cntl = INREG(SURFACE_CNTL); in radeon_save_state()
1325 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP); in radeon_save_state()
1326 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP); in radeon_save_state()
1327 save->fp_gen_cntl = INREG(FP_GEN_CNTL); in radeon_save_state()
1328 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID); in radeon_save_state()
1329 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH); in radeon_save_state()
1330 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID); in radeon_save_state()
1331 save->fp_vert_stretch = INREG(FP_VERT_STRETCH); in radeon_save_state()
1332 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL); in radeon_save_state()
1333 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL); in radeon_save_state()
1334 save->tmds_crc = INREG(TMDS_CRC); in radeon_save_state()
1335 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL); in radeon_save_state()
1336 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL); in radeon_save_state()
1339 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f; in radeon_save_state()
1341 save->ppll_div_3 = INPLL(PPLL_DIV_3); in radeon_save_state()
1342 save->ppll_ref_div = INPLL(PPLL_REF_DIV); in radeon_save_state()
1353 if (rinfo->is_mobility) { in radeon_write_pll_regs()
1361 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()
1362 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()
1368 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()
1386 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()
1393 rinfo->family == CHIP_FAMILY_RS300 || in radeon_write_pll_regs()
1394 rinfo->family == CHIP_FAMILY_RS400 || in radeon_write_pll_regs()
1395 rinfo->family == CHIP_FAMILY_RS480) { in radeon_write_pll_regs()
1396 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { in radeon_write_pll_regs()
1400 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()
1404 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), in radeon_write_pll_regs()
1408 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()
1411 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); in radeon_write_pll_regs()
1412 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
1449 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl); in radeon_lvds_timer_func()
1474 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]); in radeon_write_mode()
1475 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]); in radeon_write_mode()
1476 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]); in radeon_write_mode()
1479 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); in radeon_write_mode()
1480 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, in radeon_write_mode()
1482 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl); in radeon_write_mode()
1483 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); in radeon_write_mode()
1484 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); in radeon_write_mode()
1485 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); in radeon_write_mode()
1486 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); in radeon_write_mode()
1487 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); in radeon_write_mode()
1490 OUTREG(CRTC_PITCH, mode->crtc_pitch); in radeon_write_mode()
1491 OUTREG(SURFACE_CNTL, mode->surface_cntl); in radeon_write_mode()
1497 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp); in radeon_write_mode()
1498 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp); in radeon_write_mode()
1499 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid); in radeon_write_mode()
1500 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid); in radeon_write_mode()
1501 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch); in radeon_write_mode()
1502 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch); in radeon_write_mode()
1503 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl); in radeon_write_mode()
1504 OUTREG(TMDS_CRC, mode->tmds_crc); in radeon_write_mode()
1505 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl); in radeon_write_mode()
1512 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl); in radeon_write_mode()
1555 while (rinfo->has_CRTC2) { in radeon_calc_pll_regs()
1566 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) { in radeon_calc_pll_regs()
1577 /* sourced from CRTC2 -> exit */ in radeon_calc_pll_regs()
1588 if (freq > rinfo->pll.ppll_max) in radeon_calc_pll_regs()
1589 freq = rinfo->pll.ppll_max; in radeon_calc_pll_regs()
1590 if (freq*12 < rinfo->pll.ppll_min) in radeon_calc_pll_regs()
1591 freq = rinfo->pll.ppll_min / 12; in radeon_calc_pll_regs()
1593 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max); in radeon_calc_pll_regs()
1595 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_calc_pll_regs()
1596 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1600 if (uses_dvo && (post_div->divider & 1)) in radeon_calc_pll_regs()
1602 if (pll_output_freq >= rinfo->pll.ppll_min && in radeon_calc_pll_regs()
1603 pll_output_freq <= rinfo->pll.ppll_max) in radeon_calc_pll_regs()
1608 given by the terminal post_div->bitvalue */ in radeon_calc_pll_regs()
1609 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1610 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs()
1611 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1614 rinfo->pll.ref_div, rinfo->pll.ref_clk, in radeon_calc_pll_regs()
1618 given by the terminal post_div->bitvalue */ in radeon_calc_pll_regs()
1619 if ( !post_div->divider ) { in radeon_calc_pll_regs()
1620 post_div = &post_divs[post_div->bitvalue]; in radeon_calc_pll_regs()
1621 pll_output_freq = post_div->divider * freq; in radeon_calc_pll_regs()
1624 rinfo->pll.ref_div, rinfo->pll.ref_clk, in radeon_calc_pll_regs()
1627 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, in radeon_calc_pll_regs()
1628 rinfo->pll.ref_clk); in radeon_calc_pll_regs()
1629 regs->ppll_ref_div = rinfo->pll.ref_div; in radeon_calc_pll_regs()
1630 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); in radeon_calc_pll_regs()
1632 pr_debug("post div = 0x%x\n", post_div->bitvalue); in radeon_calc_pll_regs()
1634 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3); in radeon_calc_pll_regs()
1639 struct radeonfb_info *rinfo = info->par; in radeonfb_set_par()
1640 struct fb_var_screeninfo *mode = &info->var; in radeonfb_set_par()
1657 return -ENOMEM; in radeonfb_set_par()
1664 hSyncStart = mode->xres + mode->right_margin; in radeonfb_set_par()
1665 hSyncEnd = hSyncStart + mode->hsync_len; in radeonfb_set_par()
1666 hTotal = hSyncEnd + mode->left_margin; in radeonfb_set_par()
1668 vSyncStart = mode->yres + mode->lower_margin; in radeonfb_set_par()
1669 vSyncEnd = vSyncStart + mode->vsync_len; in radeonfb_set_par()
1670 vTotal = vSyncEnd + mode->upper_margin; in radeonfb_set_par()
1671 pixClock = mode->pixclock; in radeonfb_set_par()
1673 sync = mode->sync; in radeonfb_set_par()
1678 if (rinfo->panel_info.xres < mode->xres) in radeonfb_set_par()
1679 mode->xres = rinfo->panel_info.xres; in radeonfb_set_par()
1680 if (rinfo->panel_info.yres < mode->yres) in radeonfb_set_par()
1681 mode->yres = rinfo->panel_info.yres; in radeonfb_set_par()
1683 hTotal = mode->xres + rinfo->panel_info.hblank; in radeonfb_set_par()
1684 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus; in radeonfb_set_par()
1685 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width; in radeonfb_set_par()
1687 vTotal = mode->yres + rinfo->panel_info.vblank; in radeonfb_set_par()
1688 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus; in radeonfb_set_par()
1689 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width; in radeonfb_set_par()
1691 h_sync_pol = !rinfo->panel_info.hAct_high; in radeonfb_set_par()
1692 v_sync_pol = !rinfo->panel_info.vAct_high; in radeonfb_set_par()
1694 pixClock = 100000000 / rinfo->panel_info.clock; in radeonfb_set_par()
1696 if (rinfo->panel_info.use_bios_dividers) { in radeonfb_set_par()
1698 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider | in radeonfb_set_par()
1699 (rinfo->panel_info.post_divider << 16); in radeonfb_set_par()
1700 newmode->ppll_ref_div = rinfo->panel_info.ref_divider; in radeonfb_set_par()
1711 hsync_wid = (hSyncEnd - hSyncStart) / 8; in radeonfb_set_par()
1712 vsync_wid = vSyncEnd - vSyncStart; in radeonfb_set_par()
1726 hsync_fudge = hsync_fudge_fp[format-1]; in radeonfb_set_par()
1728 hsync_fudge = hsync_adj_tab[format-1]; in radeonfb_set_par()
1730 hsync_start = hSyncStart - 8 + hsync_fudge; in radeonfb_set_par()
1732 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | in radeonfb_set_par()
1735 /* Clear auto-center etc... */ in radeonfb_set_par()
1736 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl; in radeonfb_set_par()
1737 newmode->crtc_more_cntl &= 0xfffffff0; in radeonfb_set_par()
1740 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN; in radeonfb_set_par()
1742 newmode->crtc_ext_cntl |= CRTC_CRT_ON; in radeonfb_set_par()
1744 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN | in radeonfb_set_par()
1747 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | in radeonfb_set_par()
1751 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN | in radeonfb_set_par()
1754 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) | in radeonfb_set_par()
1755 (((mode->xres / 8) - 1) << 16)); in radeonfb_set_par()
1757 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) | in radeonfb_set_par()
1760 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) | in radeonfb_set_par()
1761 ((mode->yres - 1) << 16); in radeonfb_set_par()
1763 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) | in radeonfb_set_par()
1766 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) { in radeonfb_set_par()
1768 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f) in radeonfb_set_par()
1771 /* Then, re-multiply it to get the CRTC pitch */ in radeonfb_set_par()
1772 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8); in radeonfb_set_par()
1774 newmode->crtc_pitch = (mode->xres_virtual >> 3); in radeonfb_set_par()
1776 newmode->crtc_pitch |= (newmode->crtc_pitch << 16); in radeonfb_set_par()
1783 newmode->surface_cntl = 0; in radeonfb_set_par()
1791 switch (mode->bits_per_pixel) { in radeonfb_set_par()
1793 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP; in radeonfb_set_par()
1794 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP; in radeonfb_set_par()
1798 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP; in radeonfb_set_par()
1799 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP; in radeonfb_set_par()
1806 newmode->surf_lower_bound[i] = 0; in radeonfb_set_par()
1807 newmode->surf_upper_bound[i] = 0x1f; in radeonfb_set_par()
1808 newmode->surf_info[i] = 0; in radeonfb_set_par()
1812 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid); in radeonfb_set_par()
1814 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid); in radeonfb_set_par()
1816 rinfo->bpp = mode->bits_per_pixel; in radeonfb_set_par()
1817 rinfo->depth = depth; in radeonfb_set_par()
1823 newmode->clk_cntl_index = 0x300; in radeonfb_set_par()
1829 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl; in radeonfb_set_par()
1834 if (mode->xres > rinfo->panel_info.xres) in radeonfb_set_par()
1835 mode->xres = rinfo->panel_info.xres; in radeonfb_set_par()
1836 if (mode->yres > rinfo->panel_info.yres) in radeonfb_set_par()
1837 mode->yres = rinfo->panel_info.yres; in radeonfb_set_par()
1839 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1) in radeonfb_set_par()
1841 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1) in radeonfb_set_par()
1844 if (mode->xres != rinfo->panel_info.xres) { in radeonfb_set_par()
1845 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX, in radeonfb_set_par()
1846 rinfo->panel_info.xres); in radeonfb_set_par()
1847 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) | in radeonfb_set_par()
1848 (newmode->fp_horz_stretch & in radeonfb_set_par()
1851 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND | in radeonfb_set_par()
1855 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO; in radeonfb_set_par()
1857 if (mode->yres != rinfo->panel_info.yres) { in radeonfb_set_par()
1858 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX, in radeonfb_set_par()
1859 rinfo->panel_info.yres); in radeonfb_set_par()
1860 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) | in radeonfb_set_par()
1861 (newmode->fp_vert_stretch & in radeonfb_set_par()
1863 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND | in radeonfb_set_par()
1867 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN; in radeonfb_set_par()
1869 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32) in radeonfb_set_par()
1879 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR | in radeonfb_set_par()
1884 (rinfo->family == CHIP_FAMILY_R200)) { in radeonfb_set_par()
1885 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; in radeonfb_set_par()
1887 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; in radeonfb_set_par()
1889 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; in radeonfb_set_par()
1891 newmode->fp_gen_cntl |= FP_SEL_CRTC1; in radeonfb_set_par()
1893 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl; in radeonfb_set_par()
1894 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl; in radeonfb_set_par()
1895 newmode->tmds_crc = rinfo->init_state.tmds_crc; in radeonfb_set_par()
1896 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl; in radeonfb_set_par()
1899 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON); in radeonfb_set_par()
1900 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN); in radeonfb_set_par()
1903 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN); in radeonfb_set_par()
1904 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST); in radeonfb_set_par()
1907 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2) in radeonfb_set_par()
1908 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN; in radeonfb_set_par()
1910 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN; in radeonfb_set_par()
1911 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON; in radeonfb_set_par()
1914 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) | in radeonfb_set_par()
1915 (((mode->xres / 8) - 1) << 16)); in radeonfb_set_par()
1916 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) | in radeonfb_set_par()
1917 ((mode->yres - 1) << 16); in radeonfb_set_par()
1918 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) | in radeonfb_set_par()
1920 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) | in radeonfb_set_par()
1925 if (!rinfo->asleep) { in radeonfb_set_par()
1926 memcpy(&rinfo->state, newmode, sizeof(*newmode)); in radeonfb_set_par()
1929 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) in radeonfb_set_par()
1933 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) in radeonfb_set_par()
1934 info->fix.line_length = rinfo->pitch*64; in radeonfb_set_par()
1936 info->fix.line_length = mode->xres_virtual in radeonfb_set_par()
1937 * ((mode->bits_per_pixel + 1) / 8); in radeonfb_set_par()
1938 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR in radeonfb_set_par()
1943 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres, in radeonfb_set_par()
1944 rinfo->depth, info->fix.line_length); in radeonfb_set_par()
1970 struct fb_info *info = rinfo->info; in radeon_set_fbinfo()
1972 info->par = rinfo; in radeon_set_fbinfo()
1973 info->pseudo_palette = rinfo->pseudo_palette; in radeon_set_fbinfo()
1974 info->flags = FBINFO_DEFAULT in radeon_set_fbinfo()
1979 info->fbops = &radeonfb_ops; in radeon_set_fbinfo()
1980 info->screen_base = rinfo->fb_base; in radeon_set_fbinfo()
1981 info->screen_size = rinfo->mapped_vram; in radeon_set_fbinfo()
1983 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id)); in radeon_set_fbinfo()
1984 info->fix.smem_start = rinfo->fb_base_phys; in radeon_set_fbinfo()
1985 info->fix.smem_len = rinfo->video_ram; in radeon_set_fbinfo()
1986 info->fix.type = FB_TYPE_PACKED_PIXELS; in radeon_set_fbinfo()
1987 info->fix.visual = FB_VISUAL_PSEUDOCOLOR; in radeon_set_fbinfo()
1988 info->fix.xpanstep = 8; in radeon_set_fbinfo()
1989 info->fix.ypanstep = 1; in radeon_set_fbinfo()
1990 info->fix.ywrapstep = 0; in radeon_set_fbinfo()
1991 info->fix.type_aux = 0; in radeon_set_fbinfo()
1992 info->fix.mmio_start = rinfo->mmio_base_phys; in radeon_set_fbinfo()
1993 info->fix.mmio_len = RADEON_REGSIZE; in radeon_set_fbinfo()
1994 info->fix.accel = FB_ACCEL_ATI_RADEON; in radeon_set_fbinfo()
1996 fb_alloc_cmap(&info->cmap, 256, 0); in radeon_set_fbinfo()
1999 info->flags |= FBINFO_HWACCEL_DISABLED; in radeon_set_fbinfo()
2010 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
2025 if (rinfo->has_CRTC2) { in fixup_memory_mappings()
2042 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16)); in fixup_memory_mappings()
2043 rinfo->fb_local_base = aper_base; in fixup_memory_mappings()
2046 rinfo->fb_local_base = 0; in fixup_memory_mappings()
2062 /* Fixup the display base addresses & engine offsets while we in fixup_memory_mappings()
2067 if (rinfo->has_CRTC2) in fixup_memory_mappings()
2072 if (rinfo->has_CRTC2) in fixup_memory_mappings()
2081 if (rinfo->has_CRTC2) in fixup_memory_mappings()
2086 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16), in fixup_memory_mappings()
2097 if ((rinfo->family == CHIP_FAMILY_RS100) || in radeon_identify_vram()
2098 (rinfo->family == CHIP_FAMILY_RS200) || in radeon_identify_vram()
2099 (rinfo->family == CHIP_FAMILY_RS300) || in radeon_identify_vram()
2100 (rinfo->family == CHIP_FAMILY_RC410) || in radeon_identify_vram()
2101 (rinfo->family == CHIP_FAMILY_RS400) || in radeon_identify_vram()
2102 (rinfo->family == CHIP_FAMILY_RS480) ) { in radeon_identify_vram()
2104 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); in radeon_identify_vram()
2115 if ((rinfo->family == CHIP_FAMILY_RS100) || in radeon_identify_vram()
2116 (rinfo->family == CHIP_FAMILY_RS200)) { in radeon_identify_vram()
2128 rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK; in radeon_identify_vram()
2134 if (rinfo->video_ram == 0) { in radeon_identify_vram()
2135 switch (rinfo->pdev->device) { in radeon_identify_vram()
2138 rinfo->video_ram = 8192 * 1024; in radeon_identify_vram()
2149 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) || in radeon_identify_vram()
2151 rinfo->vram_ddr = 1; in radeon_identify_vram()
2153 rinfo->vram_ddr = 0; in radeon_identify_vram()
2159 case 0: rinfo->vram_width = 64; break; in radeon_identify_vram()
2160 case 1: rinfo->vram_width = 128; break; in radeon_identify_vram()
2161 case 2: rinfo->vram_width = 256; break; in radeon_identify_vram()
2162 default: rinfo->vram_width = 128; break; in radeon_identify_vram()
2164 } else if ((rinfo->family == CHIP_FAMILY_RV100) || in radeon_identify_vram()
2165 (rinfo->family == CHIP_FAMILY_RS100) || in radeon_identify_vram()
2166 (rinfo->family == CHIP_FAMILY_RS200)){ in radeon_identify_vram()
2168 rinfo->vram_width = 32; in radeon_identify_vram()
2170 rinfo->vram_width = 64; in radeon_identify_vram()
2173 rinfo->vram_width = 128; in radeon_identify_vram()
2175 rinfo->vram_width = 64; in radeon_identify_vram()
2183 pci_name(rinfo->pdev), in radeon_identify_vram()
2184 rinfo->video_ram / 1024, in radeon_identify_vram()
2185 rinfo->vram_ddr ? "DDR" : "SDRAM", in radeon_identify_vram()
2186 rinfo->vram_width); in radeon_identify_vram()
2205 struct radeonfb_info *rinfo = info->par; in radeon_show_edid1()
2207 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID); in radeon_show_edid1()
2217 struct radeonfb_info *rinfo = info->par; in radeon_show_edid2()
2219 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID); in radeon_show_edid2()
2246 return -ENOMEM; in radeon_kick_out_firmware_fb()
2248 ap->ranges[0].base = pci_resource_start(pdev, 0); in radeon_kick_out_firmware_fb()
2249 ap->ranges[0].size = pci_resource_len(pdev, 0); in radeon_kick_out_firmware_fb()
2277 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev); in radeonfb_pci_register()
2279 ret = -ENOMEM; in radeonfb_pci_register()
2282 rinfo = info->par; in radeonfb_pci_register()
2283 rinfo->info = info; in radeonfb_pci_register()
2284 rinfo->pdev = pdev; in radeonfb_pci_register()
2286 spin_lock_init(&rinfo->reg_lock); in radeonfb_pci_register()
2287 timer_setup(&rinfo->lvds_timer, radeon_lvds_timer_func, 0); in radeonfb_pci_register()
2289 c1 = ent->device >> 8; in radeonfb_pci_register()
2290 c2 = ent->device & 0xff; in radeonfb_pci_register()
2292 snprintf(rinfo->name, sizeof(rinfo->name), in radeonfb_pci_register()
2293 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2); in radeonfb_pci_register()
2295 snprintf(rinfo->name, sizeof(rinfo->name), in radeonfb_pci_register()
2296 "ATI Radeon %x", ent->device & 0xffff); in radeonfb_pci_register()
2298 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK; in radeonfb_pci_register()
2299 rinfo->chipset = pdev->device; in radeonfb_pci_register()
2300 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0; in radeonfb_pci_register()
2301 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0; in radeonfb_pci_register()
2302 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0; in radeonfb_pci_register()
2304 /* Set base addrs */ in radeonfb_pci_register()
2305 rinfo->fb_base_phys = pci_resource_start (pdev, 0); in radeonfb_pci_register()
2306 rinfo->mmio_base_phys = pci_resource_start (pdev, 2); in radeonfb_pci_register()
2316 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2323 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2328 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE); in radeonfb_pci_register()
2329 if (!rinfo->mmio_base) { in radeonfb_pci_register()
2331 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2332 ret = -EIO; in radeonfb_pci_register()
2336 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; in radeonfb_pci_register()
2341 rinfo->errata = 0; in radeonfb_pci_register()
2342 if (rinfo->family == CHIP_FAMILY_R300 && in radeonfb_pci_register()
2345 rinfo->errata |= CHIP_ERRATA_R300_CG; in radeonfb_pci_register()
2347 if (rinfo->family == CHIP_FAMILY_RV200 || in radeonfb_pci_register()
2348 rinfo->family == CHIP_FAMILY_RS200) in radeonfb_pci_register()
2349 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS; in radeonfb_pci_register()
2351 if (rinfo->family == CHIP_FAMILY_RV100 || in radeonfb_pci_register()
2352 rinfo->family == CHIP_FAMILY_RS100 || in radeonfb_pci_register()
2353 rinfo->family == CHIP_FAMILY_RS200) in radeonfb_pci_register()
2354 rinfo->errata |= CHIP_ERRATA_PLL_DELAY; in radeonfb_pci_register()
2357 /* On PPC, we obtain the OF device-node pointer to the firmware in radeonfb_pci_register()
2360 rinfo->of_node = pci_device_to_OF_node(pdev); in radeonfb_pci_register()
2361 if (rinfo->of_node == NULL) in radeonfb_pci_register()
2363 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2377 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram); in radeonfb_pci_register()
2380 rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys, in radeonfb_pci_register()
2381 rinfo->mapped_vram); in radeonfb_pci_register()
2382 } while (rinfo->fb_base == NULL && in radeonfb_pci_register()
2383 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM)); in radeonfb_pci_register()
2385 if (rinfo->fb_base == NULL) { in radeonfb_pci_register()
2387 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2388 ret = -EIO; in radeonfb_pci_register()
2392 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev), in radeonfb_pci_register()
2393 rinfo->mapped_vram/1024); in radeonfb_pci_register()
2406 if (!rinfo->is_mobility) in radeonfb_pci_register()
2416 if (rinfo->bios_seg == NULL) in radeonfb_pci_register()
2423 if (rinfo->bios_seg == NULL && rinfo->is_mobility) in radeonfb_pci_register()
2444 if (rinfo->mon1_EDID) in radeonfb_pci_register()
2445 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, in radeonfb_pci_register()
2447 if (rinfo->mon2_EDID) in radeonfb_pci_register()
2448 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj, in radeonfb_pci_register()
2457 radeon_save_state (rinfo, &rinfo->init_state); in radeonfb_pci_register()
2458 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs)); in radeonfb_pci_register()
2461 if (default_dynclk < -1) { in radeonfb_pci_register()
2462 /* -2 is special: means ON on mobility chips and do not in radeonfb_pci_register()
2465 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep); in radeonfb_pci_register()
2475 pci_name(rinfo->pdev)); in radeonfb_pci_register()
2480 rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys, in radeonfb_pci_register()
2481 rinfo->video_ram); in radeonfb_pci_register()
2486 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name); in radeonfb_pci_register()
2488 if (rinfo->bios_seg) in radeonfb_pci_register()
2494 iounmap(rinfo->fb_base); in radeonfb_pci_register()
2496 kfree(rinfo->mon1_EDID); in radeonfb_pci_register()
2497 kfree(rinfo->mon2_EDID); in radeonfb_pci_register()
2498 if (rinfo->mon1_modedb) in radeonfb_pci_register()
2499 fb_destroy_modedb(rinfo->mon1_modedb); in radeonfb_pci_register()
2500 fb_dealloc_cmap(&info->cmap); in radeonfb_pci_register()
2504 if (rinfo->bios_seg) in radeonfb_pci_register()
2506 iounmap(rinfo->mmio_base); in radeonfb_pci_register()
2523 struct radeonfb_info *rinfo = info->par; in radeonfb_pci_unregister()
2530 if (rinfo->mon1_EDID) in radeonfb_pci_unregister()
2531 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr); in radeonfb_pci_unregister()
2532 if (rinfo->mon2_EDID) in radeonfb_pci_unregister()
2533 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr); in radeonfb_pci_unregister()
2535 del_timer_sync(&rinfo->lvds_timer); in radeonfb_pci_unregister()
2536 arch_phys_wc_del(rinfo->wc_cookie); in radeonfb_pci_unregister()
2541 iounmap(rinfo->mmio_base); in radeonfb_pci_unregister()
2542 iounmap(rinfo->fb_base); in radeonfb_pci_unregister()
2547 kfree(rinfo->mon1_EDID); in radeonfb_pci_unregister()
2548 kfree(rinfo->mon2_EDID); in radeonfb_pci_unregister()
2549 if (rinfo->mon1_modedb) in radeonfb_pci_unregister()
2550 fb_destroy_modedb(rinfo->mon1_modedb); in radeonfb_pci_unregister()
2554 fb_dealloc_cmap(&info->cmap); in radeonfb_pci_unregister()
2621 return -ENODEV; in radeonfb_init()
2637 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2641 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2660 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");