206 	u32 val;  in set_pts()  local
209 		val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);  in set_pts()
210 		val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);  in set_pts()
211 		val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);  in set_pts()
212 		writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);  in set_pts()
214 		val = readl_relaxed(base + TEGRA_USB_PORTSC1);  in set_pts()
215 		val &= ~TEGRA_PORTSC1_RWC_BITS;  in set_pts()
216 		val &= ~TEGRA_USB_PORTSC1_PTS(~0);  in set_pts()
217 		val |= TEGRA_USB_PORTSC1_PTS(pts_val);  in set_pts()
218 		writel_relaxed(val, base + TEGRA_USB_PORTSC1);  in set_pts()
225 	u32 val;  in set_phcd()  local
228 		val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);  in set_phcd()
230 			val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;  in set_phcd()
232 			val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;  in set_phcd()
233 		writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);  in set_phcd()
235 		val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;  in set_phcd()
237 			val |= TEGRA_USB_PORTSC1_PHCD;  in set_phcd()
239 			val &= ~TEGRA_USB_PORTSC1_PHCD;  in set_phcd()
240 		writel_relaxed(val, base + TEGRA_USB_PORTSC1);  in set_phcd()
312 	u32 val;  in utmip_pad_power_on()  local
322 		val = readl_relaxed(base + UTMIP_BIAS_CFG0);  in utmip_pad_power_on()
323 		val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);  in utmip_pad_power_on()
326 			val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |  in utmip_pad_power_on()
330 			val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);  in utmip_pad_power_on()
331 			val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);  in utmip_pad_power_on()
332 			val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);  in utmip_pad_power_on()
334 		writel_relaxed(val, base + UTMIP_BIAS_CFG0);  in utmip_pad_power_on()
347 	u32 val;  in utmip_pad_power_off()  local
363 		val = readl_relaxed(base + UTMIP_BIAS_CFG0);  in utmip_pad_power_off()
364 		val |= UTMIP_OTGPD | UTMIP_BIASPD;  in utmip_pad_power_off()
365 		writel_relaxed(val, base + UTMIP_BIAS_CFG0);  in utmip_pad_power_off()
386 	u32 val;  in utmi_phy_clk_disable()  local
397 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_clk_disable()
398 		val |= USB_SUSP_SET;  in utmi_phy_clk_disable()
399 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_clk_disable()
403 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_clk_disable()
404 		val &= ~USB_SUSP_SET;  in utmi_phy_clk_disable()
405 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_clk_disable()
418 	u32 val;  in utmi_phy_clk_enable()  local
430 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_clk_enable()
431 		val |= USB_SUSP_CLR;  in utmi_phy_clk_enable()
432 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_clk_enable()
436 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_clk_enable()
437 		val &= ~USB_SUSP_CLR;  in utmi_phy_clk_enable()
438 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_clk_enable()
453 	u32 val;  in utmi_phy_power_on()  local
456 	val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
457 	val |= UTMIP_RESET;  in utmi_phy_power_on()
458 	writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
461 		val = readl_relaxed(base + USB1_LEGACY_CTRL);  in utmi_phy_power_on()
462 		val |= USB1_NO_LEGACY_MODE;  in utmi_phy_power_on()
463 		writel_relaxed(val, base + USB1_LEGACY_CTRL);  in utmi_phy_power_on()
466 	val = readl_relaxed(base + UTMIP_TX_CFG0);  in utmi_phy_power_on()
467 	val |= UTMIP_FS_PREABMLE_J;  in utmi_phy_power_on()
468 	writel_relaxed(val, base + UTMIP_TX_CFG0);  in utmi_phy_power_on()
470 	val = readl_relaxed(base + UTMIP_HSRX_CFG0);  in utmi_phy_power_on()
471 	val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));  in utmi_phy_power_on()
472 	val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);  in utmi_phy_power_on()
473 	val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);  in utmi_phy_power_on()
474 	writel_relaxed(val, base + UTMIP_HSRX_CFG0);  in utmi_phy_power_on()
476 	val = readl_relaxed(base + UTMIP_HSRX_CFG1);  in utmi_phy_power_on()
477 	val &= ~UTMIP_HS_SYNC_START_DLY(~0);  in utmi_phy_power_on()
478 	val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);  in utmi_phy_power_on()
479 	writel_relaxed(val, base + UTMIP_HSRX_CFG1);  in utmi_phy_power_on()
481 	val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);  in utmi_phy_power_on()
482 	val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);  in utmi_phy_power_on()
483 	val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);  in utmi_phy_power_on()
484 	writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);  in utmi_phy_power_on()
486 	val = readl_relaxed(base + UTMIP_MISC_CFG0);  in utmi_phy_power_on()
487 	val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;  in utmi_phy_power_on()
488 	writel_relaxed(val, base + UTMIP_MISC_CFG0);  in utmi_phy_power_on()
491 		val = readl_relaxed(base + UTMIP_MISC_CFG1);  in utmi_phy_power_on()
492 		val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |  in utmi_phy_power_on()
494 		val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |  in utmi_phy_power_on()
496 		writel_relaxed(val, base + UTMIP_MISC_CFG1);  in utmi_phy_power_on()
498 		val = readl_relaxed(base + UTMIP_PLL_CFG1);  in utmi_phy_power_on()
499 		val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |  in utmi_phy_power_on()
501 		val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |  in utmi_phy_power_on()
503 		writel_relaxed(val, base + UTMIP_PLL_CFG1);  in utmi_phy_power_on()
507 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
508 		val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);  in utmi_phy_power_on()
509 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
511 		val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_on()
512 		val &= ~UTMIP_PD_CHRG;  in utmi_phy_power_on()
513 		writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_on()
515 		val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_on()
516 		val |= UTMIP_PD_CHRG;  in utmi_phy_power_on()
517 		writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_on()
524 	val = readl_relaxed(base + UTMIP_XCVR_CFG0);  in utmi_phy_power_on()
525 	val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |  in utmi_phy_power_on()
531 		val |= UTMIP_XCVR_SETUP(config->xcvr_setup);  in utmi_phy_power_on()
532 		val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);  in utmi_phy_power_on()
534 	val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);  in utmi_phy_power_on()
535 	val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);  in utmi_phy_power_on()
538 		val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));  in utmi_phy_power_on()
539 		val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);  in utmi_phy_power_on()
540 		val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);  in utmi_phy_power_on()
542 	writel_relaxed(val, base + UTMIP_XCVR_CFG0);  in utmi_phy_power_on()
544 	val = readl_relaxed(base + UTMIP_XCVR_CFG1);  in utmi_phy_power_on()
545 	val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |  in utmi_phy_power_on()
547 	val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);  in utmi_phy_power_on()
548 	writel_relaxed(val, base + UTMIP_XCVR_CFG1);  in utmi_phy_power_on()
550 	val = readl_relaxed(base + UTMIP_BIAS_CFG1);  in utmi_phy_power_on()
551 	val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);  in utmi_phy_power_on()
552 	val |= UTMIP_BIAS_PDTRK_COUNT(0x5);  in utmi_phy_power_on()
553 	writel_relaxed(val, base + UTMIP_BIAS_CFG1);  in utmi_phy_power_on()
555 	val = readl_relaxed(base + UTMIP_SPARE_CFG0);  in utmi_phy_power_on()
557 		val |= FUSE_SETUP_SEL;  in utmi_phy_power_on()
559 		val &= ~FUSE_SETUP_SEL;  in utmi_phy_power_on()
560 	writel_relaxed(val, base + UTMIP_SPARE_CFG0);  in utmi_phy_power_on()
563 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
564 		val |= UTMIP_PHY_ENABLE;  in utmi_phy_power_on()
565 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
568 	val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
569 	val &= ~UTMIP_RESET;  in utmi_phy_power_on()
570 	writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
573 		val = readl_relaxed(base + USB1_LEGACY_CTRL);  in utmi_phy_power_on()
574 		val &= ~USB1_VBUS_SENSE_CTL_MASK;  in utmi_phy_power_on()
575 		val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;  in utmi_phy_power_on()
576 		writel_relaxed(val, base + USB1_LEGACY_CTRL);  in utmi_phy_power_on()
578 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_on()
579 		val &= ~USB_SUSP_SET;  in utmi_phy_power_on()
580 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
586 		val = readl_relaxed(base + USB_USBMODE);  in utmi_phy_power_on()
587 		val &= ~USB_USBMODE_MASK;  in utmi_phy_power_on()
589 			val |= USB_USBMODE_HOST;  in utmi_phy_power_on()
591 			val |= USB_USBMODE_DEVICE;  in utmi_phy_power_on()
592 		writel_relaxed(val, base + USB_USBMODE);  in utmi_phy_power_on()
604 	u32 val;  in utmi_phy_power_off()  local
609 		val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_off()
610 		val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);  in utmi_phy_power_off()
611 		val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);  in utmi_phy_power_off()
612 		writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_off()
615 	val = readl_relaxed(base + USB_SUSP_CTRL);  in utmi_phy_power_off()
616 	val |= UTMIP_RESET;  in utmi_phy_power_off()
617 	writel_relaxed(val, base + USB_SUSP_CTRL);  in utmi_phy_power_off()
619 	val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_off()
620 	val |= UTMIP_PD_CHRG;  in utmi_phy_power_off()
621 	writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_off()
623 	val = readl_relaxed(base + UTMIP_XCVR_CFG0);  in utmi_phy_power_off()
624 	val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |  in utmi_phy_power_off()
626 	writel_relaxed(val, base + UTMIP_XCVR_CFG0);  in utmi_phy_power_off()
628 	val = readl_relaxed(base + UTMIP_XCVR_CFG1);  in utmi_phy_power_off()
629 	val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |  in utmi_phy_power_off()
631 	writel_relaxed(val, base + UTMIP_XCVR_CFG1);  in utmi_phy_power_off()
639 	u32 val;  in utmi_phy_preresume()  local
641 	val = readl_relaxed(base + UTMIP_TX_CFG0);  in utmi_phy_preresume()
642 	val |= UTMIP_HS_DISCON_DISABLE;  in utmi_phy_preresume()
643 	writel_relaxed(val, base + UTMIP_TX_CFG0);  in utmi_phy_preresume()
649 	u32 val;  in utmi_phy_postresume()  local
651 	val = readl_relaxed(base + UTMIP_TX_CFG0);  in utmi_phy_postresume()
652 	val &= ~UTMIP_HS_DISCON_DISABLE;  in utmi_phy_postresume()
653 	writel_relaxed(val, base + UTMIP_TX_CFG0);  in utmi_phy_postresume()
660 	u32 val;  in utmi_phy_restore_start()  local
662 	val = readl_relaxed(base + UTMIP_MISC_CFG0);  in utmi_phy_restore_start()
663 	val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);  in utmi_phy_restore_start()
665 		val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;  in utmi_phy_restore_start()
667 		val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;  in utmi_phy_restore_start()
668 	writel_relaxed(val, base + UTMIP_MISC_CFG0);  in utmi_phy_restore_start()
671 	val = readl_relaxed(base + UTMIP_MISC_CFG0);  in utmi_phy_restore_start()
672 	val |= UTMIP_DPDM_OBSERVE;  in utmi_phy_restore_start()
673 	writel_relaxed(val, base + UTMIP_MISC_CFG0);  in utmi_phy_restore_start()
680 	u32 val;  in utmi_phy_restore_end()  local
682 	val = readl_relaxed(base + UTMIP_MISC_CFG0);  in utmi_phy_restore_end()
683 	val &= ~UTMIP_DPDM_OBSERVE;  in utmi_phy_restore_end()
684 	writel_relaxed(val, base + UTMIP_MISC_CFG0);  in utmi_phy_restore_end()
691 	u32 val;  in ulpi_phy_power_on()  local
706 	val = readl_relaxed(base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
707 	val |= UHSIC_RESET;  in ulpi_phy_power_on()
708 	writel_relaxed(val, base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
710 	val = readl_relaxed(base + ULPI_TIMING_CTRL_0);  in ulpi_phy_power_on()
711 	val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;  in ulpi_phy_power_on()
712 	writel_relaxed(val, base + ULPI_TIMING_CTRL_0);  in ulpi_phy_power_on()
714 	val = readl_relaxed(base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
715 	val |= ULPI_PHY_ENABLE;  in ulpi_phy_power_on()
716 	writel_relaxed(val, base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
718 	val = 0;  in ulpi_phy_power_on()
719 	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);  in ulpi_phy_power_on()
721 	val |= ULPI_DATA_TRIMMER_SEL(4);  in ulpi_phy_power_on()
722 	val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);  in ulpi_phy_power_on()
723 	val |= ULPI_DIR_TRIMMER_SEL(4);  in ulpi_phy_power_on()
724 	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);  in ulpi_phy_power_on()
727 	val |= ULPI_DATA_TRIMMER_LOAD;  in ulpi_phy_power_on()
728 	val |= ULPI_STPDIRNXT_TRIMMER_LOAD;  in ulpi_phy_power_on()
729 	val |= ULPI_DIR_TRIMMER_LOAD;  in ulpi_phy_power_on()
730 	writel_relaxed(val, base + ULPI_TIMING_CTRL_1);  in ulpi_phy_power_on()
745 	val = readl_relaxed(base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
746 	val |= USB_SUSP_CLR;  in ulpi_phy_power_on()
747 	writel_relaxed(val, base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
750 	val = readl_relaxed(base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
751 	val &= ~USB_SUSP_CLR;  in ulpi_phy_power_on()
752 	writel_relaxed(val, base + USB_SUSP_CTRL);  in ulpi_phy_power_on()