Lines Matching +full:max +full:- +full:link +full:- +full:speed
1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/io-64-nonatomic-lo-hi.h>
21 /* Code sharing between pci-quirks and xhci hcd */
22 #include "xhci-ext-caps.h"
23 #include "pci-quirks.h"
28 /* Max number of USB devices for any host controller - limit in section 6.1 */
30 /* Section 5.3.3 - MaxPorts */
40 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
42 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
43 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
44 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
45 * @hcc_params: HCCPARAMS - Capability Parameters
46 * @db_off: DBOFF - Doorbell array offset
47 * @run_regs_off: RTSOFF - Runtime register space offset
59 /* Reserved up to (CAPLENGTH - 0x1C) */
63 /* bits 7:0 - how long is the Capabilities register */
68 /* HCSPARAMS1 - hcs_params1 - bitmasks */
69 /* bits 0:7, Max Device Slots */
72 /* bits 8:18, Max Interrupters */
74 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
77 /* HCSPARAMS2 - hcs_params2 - bitmasks */
81 /* bits 4:7, max number of Event Ring segments */
84 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
88 /* HCSPARAMS3 - hcs_params3 - bitmasks */
89 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
91 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
94 /* HCCPARAMS - hcc_params - bitmasks */
95 /* true: HC can use 64-bit address pointers */
99 /* true: HC uses 64-byte Device Context structures
100 * FIXME 64-byte context structures aren't supported yet.
113 /* true: HC supports Stopped - Short Packet */
117 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
119 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
124 /* db_off bitmask - bits 0:1 reserved */
127 /* run_regs_off bitmask - bits 0:4 reserved */
130 /* HCCPARAMS2 - hcc_params2 - bitmasks */
133 /* true: HC supports Configure endpoint command Max exit latency too large */
155 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
156 * @command: USBCMD - xHC command register
157 * @status: USBSTS - xHC status register
162 * @cmd_ring: CRP - 64-bit Command Ring Pointer
163 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
164 * @config_reg: CONFIG - Configure Register
165 * @port_status_base: PORTSCn - base address for Port Status and Control
168 * register, a Port Link Info register, and a reserved
170 * @port_power_base: PORTPMSCn - base address for
172 * @port_link_base: PORTLIn - base address for Port Link Info (current
173 * Link PM state and control) for USB 2.1 and USB 3.0
184 /* rsvd: offset 0x20-2F */
188 /* rsvd: offset 0x3C-3FF */
195 /* registers for ports 2-255 */
199 /* USBCMD - USB command - command bitmasks */
200 /* start/stop HC execution - do not write unless HC is halted*/
202 /* Reset HC - resets internal HC state machine and all registers (except
207 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
209 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
212 /* light reset (port status stays unchanged) - reset completed when this is 0 */
217 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
219 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
220 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
222 * disabled, or powered-off state.
229 /* IMAN - Interrupt Management Register */
233 /* USBSTS - USB status - status bitmasks */
234 /* HC not running - set to 1 when run/stop bit is cleared. */
238 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
243 /* save state status - '1' means xHC is saving state */
245 /* restore state status - '1' means xHC is restoring state */
251 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
256 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
267 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
271 /* stop ring immediately - abort the currently executing command */
276 /* Command Ring pointer - bit mask for the lower 32 bits. */
279 /* CONFIG - Configure Register - config_reg bitmasks */
280 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
286 /* bits 10:31 - reserved and should be preserved */
288 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
294 /* true: port has an over-current condition */
298 /* Port Link State - bits 5:8
299 * A read gives the current link PM state of the port,
300 * a write with Link State Write Strobe set sets the link state.
319 /* bits 10:13 indicate device speed:
320 * 0 - undefined speed - port hasn't be initialized by a reset yet
321 * 1 - full speed
322 * 2 - low speed
323 * 3 - high speed
324 * 4 - super speed
325 * 5-15 reserved
342 /* Bits 20:23 in the Slot Context are the speed for the device */
353 /* Port Link State Write Strobe - set this when changing link state */
361 * also resets the link, forcing the device through the link training sequence.
365 /* true: over-current change */
367 /* true: reset change - 1 to 0 transition of PORT_RESET */
369 /* port link status change - set on some port link state transitions:
371 * ------------------------------------------------------------------------------
372 * - U3 to Resume Wakeup signaling from a device
373 * - Resume to Recovery to U0 USB 3.0 device resume
374 * - Resume to U0 USB 2.0 device resume
375 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
376 * - U3 to U0 Software resume of USB 2.0 device complete
377 * - U2 to U0 L1 resume of USB 2.1 device complete
378 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
379 * - U0 to disabled L1 entry error with USB 2.1 device
380 * - Any state to inactive Error on USB 3.0 port
383 /* port configure error change - port failed to configure its link partner */
389 /* Cold Attach Status - xHC can set this bit to report device attached during
398 /* wake on over-current (enable) */
401 /* true: device is non-removable - for USB 3.0 roothub emulation */
403 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
406 /* We mark duplicate entries with -1 */
407 #define DUPLICATE_ENTRY ((u8)(-1))
409 /* Port Power Management Status and Control - port_power_base bitmasks */
431 /* USB3 Protocol PORTLI Port Link Information */
457 * to complete link training. usually link trainig completes much faster
464 * struct xhci_intr_reg - Interrupt Register Set
465 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
467 * @irq_control: IMOD - Interrupt Moderation Register.
473 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
492 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
503 /* Counter used to count down the time to the next interrupt - HW use only */
511 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
515 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
524 * MFINDEX - current microframe number
539 * Bits 0 - 7: Endpoint target
540 * Bits 8 - 15: RsvdZ
541 * Bits 16 - 31: Stream ID
558 * @port_info: Port offset, count, and protocol-defined information.
607 * @dev_info: Route string, device speed, hub info, and last valid endpoint
608 * @dev_info2: Max exit latency for device number, root hub port number
612 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
613 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
626 /* Route String - 0:19 */
628 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
632 /* Is this LS/FS device connected through a HS hub? - bit 25 */
634 /* Set if the device is a hub - bit 26 */
636 /* Index of the last valid endpoint context in this device context - 27:31 */
639 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
644 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
655 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
656 * The Slot ID of the hub that isolates the high speed signaling from
657 * this low or full-speed device. '0' if attached to root hub port.
661 * The number of the downstream facing port of the high-speed hub
662 * '0' if the device is not low or full speed.
669 /* USB device address - assigned by the HC */
685 * @ep_info2: information on endpoint type, max packet size, max burst size,
688 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
694 * max payload within an Endpoint Service Interval Time (ESIT).
696 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
697 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
705 /* offset 0x14 - 0x1f reserved for HC internal use */
711 * Endpoint State - bits 0:2
712 * 0 - disabled
713 * 1 - running
714 * 2 - halted due to halt condition - ok to manipulate endpoint ring
715 * 3 - stopped
716 * 4 - TRB error
717 * 5-7 - reserved
725 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
727 /* Mult - Max number of burtst within an interval, in EP companion desc. */
730 /* bits 10:14 are Max Primary Streams */
732 /* Interval - period between requests to an endpoint - 125u increments. */
746 * Force Event - generate transfer events for all TRBs for this endpoint
761 /* bit 7 is Host Initiate Disable - for disabling stream selection */
793 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
795 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
798 * It's useful to pre-allocate these for commands that cannot fail due to
799 * out-of-memory errors, like freeing streams.
820 /* 64-bit stream ring address, cycle state, and stream type */
822 /* offset 0x14 - 0x1f reserved for HC internal use */
826 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
862 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
866 /* ep_interval is zero-based */
868 /* mult and num_packets are one-based */
886 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
915 /* Percentage of bus bandwidth reserved for non-periodic transfers */
941 /* ---- Related to URB cancellation ---- */
977 /* Sorted by max packet size.
978 * Head of the list is the greatest max packet size.
981 /* How many endpoints of each speed are present. */
1022 #define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
1024 /* The current max exit latency for the enabled USB3 link states. */
1034 * If a high speed hub is attached to the roothub, each TT associated with that
1055 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1058 /* 64-bit device addresses; we only write 32-bit addresses */
1063 /* TODO: write function to set the 64-bit device DMA address */
1071 /* 64-bit buffer address, or immediate data */
1085 /* Completion Code - only applicable for some types of TRBs */
1183 return "Stopped - Length Invalid"; in xhci_trb_comp_code_string()
1185 return "Stopped - Short Packet"; in xhci_trb_comp_code_string()
1187 return "Max Exit Latency Too Large Error"; in xhci_trb_comp_code_string()
1206 /* 64-bit segment pointer*/
1225 /* Address device - disable SetAddress */
1228 /* Configure Endpoint - Deconfigure */
1231 /* Stop Ring - Transfer State Preserve */
1263 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1264 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1276 /* Link TRB specific fields */
1280 /* Port ID - bits 31:24 */
1286 /* transfer_len bitmasks - bits 0:16 */
1288 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1293 /* Interrupter Target - which MSI-X vector to target the completion event at */
1300 /* Cycle bit - indicates TRB ownership by HC or HCD */
1338 struct xhci_link_trb link; member
1362 /* Transfer Ring No-op (not for the command ring) */
1391 /* Force Header Command - generate a transaction or link management packet */
1393 /* No-op Command - not for transfer rings */
1395 /* TRB IDs 24-31 reserved */
1409 /* Device Notification Event - device sent function wake notification */
1411 /* MFINDEX Wrap Event - microframe counter wrapped */
1413 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1415 /* Nec vendor-specific command completion event. */
1434 return "Link"; in xhci_trb_type_string()
1438 return "No-Op"; in xhci_trb_type_string()
1468 return "No-Op Command"; in xhci_trb_type_string()
1495 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1506 * since the command ring is 64-byte aligned.
1510 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1511 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1518 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1519 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1527 /* Max packet sized bounce buffer for td-fragmant alignment */
1620 /* 64-bit event ring segment address */
1630 /* xhci->event_ring keeps track of segment dma addresses */
1687 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1707 u32 *psi; /* array of protocol speed ID entries */
1745 /* Cached register copies of read-only HC data */
1764 /* 4KB min, 128MB max */
1768 /* msi-x vectors */
1815 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1818 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1821 * they see this status (any time they drop and re-acquire xhci->lock).
1909 /* platform-specific data -- must come last */
1930 primary_hcd = hcd->primary_hcd; in hcd_to_xhci()
1932 return (struct xhci_hcd *) (primary_hcd->hcd_priv); in hcd_to_xhci()
1937 return xhci->main_hcd; in xhci_to_hcd()
1941 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1943 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1945 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1947 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1949 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1954 * Some xHCI implementations may support 64-bit address pointers. Registers
1955 * with 64-bit address pointers should be written to with dword accesses by
1957 * xHCI implementations that do not support 64-bit address pointers will ignore
1973 return xhci->quirks & XHCI_LINK_TRB_QUIRK; in xhci_link_trb_quirk()
2181 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, in xhci_urb_to_transfer_ring()
2182 xhci_get_endpoint_index(&urb->ep->desc), in xhci_urb_to_transfer_ring()
2183 urb->stream_id); in xhci_urb_to_transfer_ring()
2193 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) && in xhci_urb_suitable_for_idt()
2194 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE && in xhci_urb_suitable_for_idt()
2195 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE && in xhci_urb_suitable_for_idt()
2196 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) && in xhci_urb_suitable_for_idt()
2197 !urb->num_sgs) in xhci_urb_suitable_for_idt()
2228 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", in xhci_decode_trb()
2413 "%s: ctx %08x%08x slot %d speed %d flags %c", in xhci_decode_trb()
2431 "type '%s' -> raw %08x %08x %08x %08x", in xhci_decode_trb()
2472 u32 speed; in xhci_decode_slot_context() local
2477 speed = info & DEV_SPEED; in xhci_decode_slot_context()
2484 switch (speed) { in xhci_decode_slot_context()
2486 s = "full-speed"; in xhci_decode_slot_context()
2489 s = "low-speed"; in xhci_decode_slot_context()
2492 s = "high-speed"; in xhci_decode_slot_context()
2495 s = "super-speed"; in xhci_decode_slot_context()
2498 s = "super-speed plus"; in xhci_decode_slot_context()
2501 s = "UNKNOWN speed"; in xhci_decode_slot_context()
2503 mtt ? " multi-TT" : "", in xhci_decode_slot_context()
2560 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ", in xhci_decode_portsc()
2561 portsc & PORT_POWER ? "Powered" : "Powered-off", in xhci_decode_portsc()
2562 portsc & PORT_CONNECT ? "Connected" : "Not-connected", in xhci_decode_portsc()
2570 ret += sprintf(str + ret, "In-Reset "); in xhci_decode_portsc()
2737 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", in xhci_decode_ep_context()
2741 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", in xhci_decode_ep_context()