Lines Matching refs:temp
60 u32 temp; in xhci_create_usb3_bos_desc() local
99 temp = readl(&xhci->cap_regs->hcc_params); in xhci_create_usb3_bos_desc()
100 if (HCC_LTC(temp)) in xhci_create_usb3_bos_desc()
105 temp = readl(&xhci->cap_regs->hcs_params3); in xhci_create_usb3_bos_desc()
106 buf[12] = HCS_U1_LATENCY(temp); in xhci_create_usb3_bos_desc()
107 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]); in xhci_create_usb3_bos_desc()
172 u16 temp; in xhci_common_hub_descriptor() local
178 temp = 0; in xhci_common_hub_descriptor()
181 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
183 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
186 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
189 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
197 u16 temp; in xhci_usb2_hub_descriptor() local
207 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
208 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
574 u32 temp; in xhci_set_port_power() local
578 temp = readl(port->addr); in xhci_set_port_power()
581 hcd->self.busnum, index + 1, on ? "ON" : "OFF", temp); in xhci_set_port_power()
583 temp = xhci_port_state_to_neutral(temp); in xhci_set_port_power()
587 writel(temp | PORT_POWER, port->addr); in xhci_set_port_power()
591 writel(temp & ~PORT_POWER, port->addr); in xhci_set_port_power()
595 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_set_port_power()
597 if (temp) in xhci_set_port_power()
606 u32 temp; in xhci_port_set_test_mode() local
611 temp = readl(port->addr + PORTPMSC); in xhci_port_set_test_mode()
612 temp |= test_mode << PORT_TEST_MODE_SHIFT; in xhci_port_set_test_mode()
613 writel(temp, port->addr + PORTPMSC); in xhci_port_set_test_mode()
683 u32 temp; in xhci_set_link_state() local
687 temp = xhci_port_state_to_neutral(portsc); in xhci_set_link_state()
688 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
689 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
690 writel(temp, port->addr); in xhci_set_link_state()
694 portsc, temp); in xhci_set_link_state()
700 u32 temp; in xhci_set_remote_wake_mask() local
702 temp = readl(port->addr); in xhci_set_remote_wake_mask()
703 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
706 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
708 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
711 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
713 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
716 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
718 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
720 writel(temp, port->addr); in xhci_set_remote_wake_mask()
727 u32 temp; in xhci_test_and_clear_bit() local
729 temp = readl(port->addr); in xhci_test_and_clear_bit()
730 if (temp & port_bit) { in xhci_test_and_clear_bit()
731 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
732 temp |= port_bit; in xhci_test_and_clear_bit()
733 writel(temp, port->addr); in xhci_test_and_clear_bit()
1096 u32 temp, status; in xhci_hub_control() local
1147 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1148 if (temp == ~(u32)0) { in xhci_hub_control()
1153 trace_xhci_get_port_status(wIndex, temp); in xhci_hub_control()
1154 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1160 hcd->self.busnum, wIndex + 1, temp, status); in xhci_hub_control()
1173 status = xhci_get_ext_port_status(temp, port_li); in xhci_hub_control()
1190 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1191 if (temp == ~(u32)0) { in xhci_hub_control()
1196 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1200 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1201 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
1213 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1214 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
1215 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
1238 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1242 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1247 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1252 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
1255 writel(temp | PORT_PE, ports[wIndex]->addr); in xhci_hub_control()
1256 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1266 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1290 if ((temp & PORT_CONNECT)) { in xhci_hub_control()
1300 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1304 if (!(temp & PORT_PE)) { in xhci_hub_control()
1324 u32 pls = temp & PORT_PLS_MASK; in xhci_hub_control()
1350 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1370 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1371 if ((temp & PORT_PLS_MASK) == XDEV_U3) in xhci_hub_control()
1375 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1389 temp = (temp | PORT_RESET); in xhci_hub_control()
1390 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1392 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1394 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1399 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1401 hcd->self.busnum, wIndex + 1, temp); in xhci_hub_control()
1404 temp |= PORT_WR; in xhci_hub_control()
1405 writel(temp, ports[wIndex]->addr); in xhci_hub_control()
1406 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1411 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1412 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
1413 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
1414 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1419 temp = readl(ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1420 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
1421 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
1422 writel(temp, ports[wIndex]->addr + PORTPMSC); in xhci_hub_control()
1438 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1444 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1445 if (temp == ~(u32)0) { in xhci_hub_control()
1451 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1454 temp = readl(ports[wIndex]->addr); in xhci_hub_control()
1456 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
1457 if (temp & PORT_RESET) in xhci_hub_control()
1459 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
1460 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1496 ports[wIndex]->addr, temp); in xhci_hub_control()
1500 ports[wIndex]->addr, temp); in xhci_hub_control()
1532 u32 temp, status; in xhci_hub_status_data() local
1562 temp = readl(ports[i]->addr); in xhci_hub_status_data()
1563 if (temp == ~(u32)0) { in xhci_hub_status_data()
1568 trace_xhci_hub_status_data(i, temp); in xhci_hub_status_data()
1570 if ((temp & mask) != 0 || in xhci_hub_status_data()
1577 if ((temp & PORT_RC)) in xhci_hub_status_data()
1579 if (temp & PORT_OC) in xhci_hub_status_data()
1755 u32 temp, portsc; in xhci_bus_resume() local
1774 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1775 temp &= ~CMD_EIE; in xhci_bus_resume()
1776 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1853 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1854 temp |= CMD_EIE; in xhci_bus_resume()
1855 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1856 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()