24 #define UDC_EPCTL_ADDR		0x00	/* Endpoint control */  macro
620 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);  in pch_udc_ep_set_stall()
621 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);  in pch_udc_ep_set_stall()
623 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);  in pch_udc_ep_set_stall()
634 	pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);  in pch_udc_ep_clear_stall()
636 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);  in pch_udc_ep_clear_stall()
648 				UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);  in pch_udc_ep_set_trfr_type()
710 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);  in pch_udc_ep_set_pd()
719 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);  in pch_udc_ep_set_rrdy()
728 	pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);  in pch_udc_ep_clear_rrdy()
876 	return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);  in pch_udc_read_ep_control()
886 	return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);  in pch_udc_clear_ep_control()
917 	pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);  in pch_udc_ep_set_nak()
930 	if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))  in pch_udc_ep_clear_nak()
943 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);  in pch_udc_ep_clear_nak()
961 		pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);  in pch_udc_ep_fifo_flush()
1011 		pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);  in pch_udc_ep_disable()
1013 		pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);  in pch_udc_ep_disable()
1017 		pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);  in pch_udc_ep_disable()