Lines Matching +full:meson +full:- +full:g12a +full:- +full:usb
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2004-2016 Synopsys, Inc.
14 * 3. The names of the above-listed copyright holders may not be used
44 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_bcm_params()
46 p->host_rx_fifo_size = 774; in dwc2_set_bcm_params()
47 p->max_transfer_size = 65535; in dwc2_set_bcm_params()
48 p->max_packet_count = 511; in dwc2_set_bcm_params()
49 p->ahbcfg = 0x10; in dwc2_set_bcm_params()
54 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_his_params()
56 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; in dwc2_set_his_params()
57 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_his_params()
58 p->host_rx_fifo_size = 512; in dwc2_set_his_params()
59 p->host_nperio_tx_fifo_size = 512; in dwc2_set_his_params()
60 p->host_perio_tx_fifo_size = 512; in dwc2_set_his_params()
61 p->max_transfer_size = 65535; in dwc2_set_his_params()
62 p->max_packet_count = 511; in dwc2_set_his_params()
63 p->host_channels = 16; in dwc2_set_his_params()
64 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_his_params()
65 p->phy_utmi_width = 8; in dwc2_set_his_params()
66 p->i2c_enable = false; in dwc2_set_his_params()
67 p->reload_ctl = false; in dwc2_set_his_params()
68 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_his_params()
70 p->change_speed_quirk = true; in dwc2_set_his_params()
71 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_his_params()
76 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_s3c6400_params()
78 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_s3c6400_params()
79 p->phy_utmi_width = 8; in dwc2_set_s3c6400_params()
84 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_rk_params()
86 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; in dwc2_set_rk_params()
87 p->host_rx_fifo_size = 525; in dwc2_set_rk_params()
88 p->host_nperio_tx_fifo_size = 128; in dwc2_set_rk_params()
89 p->host_perio_tx_fifo_size = 256; in dwc2_set_rk_params()
90 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_rk_params()
92 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_rk_params()
97 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_ltq_params()
99 p->otg_cap = 2; in dwc2_set_ltq_params()
100 p->host_rx_fifo_size = 288; in dwc2_set_ltq_params()
101 p->host_nperio_tx_fifo_size = 128; in dwc2_set_ltq_params()
102 p->host_perio_tx_fifo_size = 96; in dwc2_set_ltq_params()
103 p->max_transfer_size = 65535; in dwc2_set_ltq_params()
104 p->max_packet_count = 511; in dwc2_set_ltq_params()
105 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << in dwc2_set_ltq_params()
111 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_params()
113 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; in dwc2_set_amlogic_params()
114 p->speed = DWC2_SPEED_PARAM_HIGH; in dwc2_set_amlogic_params()
115 p->host_rx_fifo_size = 512; in dwc2_set_amlogic_params()
116 p->host_nperio_tx_fifo_size = 500; in dwc2_set_amlogic_params()
117 p->host_perio_tx_fifo_size = 500; in dwc2_set_amlogic_params()
118 p->host_channels = 16; in dwc2_set_amlogic_params()
119 p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; in dwc2_set_amlogic_params()
120 p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << in dwc2_set_amlogic_params()
122 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_amlogic_params()
127 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amlogic_g12a_params()
129 p->lpm = false; in dwc2_set_amlogic_g12a_params()
130 p->lpm_clock_gating = false; in dwc2_set_amlogic_g12a_params()
131 p->besl = false; in dwc2_set_amlogic_g12a_params()
132 p->hird_threshold_en = false; in dwc2_set_amlogic_g12a_params()
137 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_amcc_params()
139 p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_amcc_params()
144 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32f4x9_fsotg_params()
146 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; in dwc2_set_stm32f4x9_fsotg_params()
147 p->speed = DWC2_SPEED_PARAM_FULL; in dwc2_set_stm32f4x9_fsotg_params()
148 p->host_rx_fifo_size = 128; in dwc2_set_stm32f4x9_fsotg_params()
149 p->host_nperio_tx_fifo_size = 96; in dwc2_set_stm32f4x9_fsotg_params()
150 p->host_perio_tx_fifo_size = 96; in dwc2_set_stm32f4x9_fsotg_params()
151 p->max_packet_count = 256; in dwc2_set_stm32f4x9_fsotg_params()
152 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_stm32f4x9_fsotg_params()
153 p->i2c_enable = false; in dwc2_set_stm32f4x9_fsotg_params()
154 p->activate_stm_fs_transceiver = true; in dwc2_set_stm32f4x9_fsotg_params()
159 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32f7_hsotg_params()
161 p->host_rx_fifo_size = 622; in dwc2_set_stm32f7_hsotg_params()
162 p->host_nperio_tx_fifo_size = 128; in dwc2_set_stm32f7_hsotg_params()
163 p->host_perio_tx_fifo_size = 256; in dwc2_set_stm32f7_hsotg_params()
168 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32mp15_fsotg_params()
170 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; in dwc2_set_stm32mp15_fsotg_params()
171 p->speed = DWC2_SPEED_PARAM_FULL; in dwc2_set_stm32mp15_fsotg_params()
172 p->host_rx_fifo_size = 128; in dwc2_set_stm32mp15_fsotg_params()
173 p->host_nperio_tx_fifo_size = 96; in dwc2_set_stm32mp15_fsotg_params()
174 p->host_perio_tx_fifo_size = 96; in dwc2_set_stm32mp15_fsotg_params()
175 p->max_packet_count = 256; in dwc2_set_stm32mp15_fsotg_params()
176 p->phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_stm32mp15_fsotg_params()
177 p->i2c_enable = false; in dwc2_set_stm32mp15_fsotg_params()
178 p->activate_stm_fs_transceiver = true; in dwc2_set_stm32mp15_fsotg_params()
179 p->activate_stm_id_vb_detection = true; in dwc2_set_stm32mp15_fsotg_params()
180 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_stm32mp15_fsotg_params()
185 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_stm32mp15_hsotg_params()
187 p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE; in dwc2_set_stm32mp15_hsotg_params()
188 p->activate_stm_id_vb_detection = !device_property_read_bool(hsotg->dev, "usb-role-switch"); in dwc2_set_stm32mp15_hsotg_params()
189 p->host_rx_fifo_size = 440; in dwc2_set_stm32mp15_hsotg_params()
190 p->host_nperio_tx_fifo_size = 256; in dwc2_set_stm32mp15_hsotg_params()
191 p->host_perio_tx_fifo_size = 256; in dwc2_set_stm32mp15_hsotg_params()
192 p->power_down = DWC2_POWER_DOWN_PARAM_NONE; in dwc2_set_stm32mp15_hsotg_params()
196 { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
197 { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
198 { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
199 { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
200 { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
202 { .compatible = "samsung,s3c6400-hsotg",
204 { .compatible = "amlogic,meson8-usb",
206 { .compatible = "amlogic,meson8b-usb",
208 { .compatible = "amlogic,meson-gxbb-usb",
210 { .compatible = "amlogic,meson-g12a-usb",
212 { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
213 { .compatible = "apm,apm82181-dwc-otg", .data = dwc2_set_amcc_params },
214 { .compatible = "st,stm32f4x9-fsotg",
216 { .compatible = "st,stm32f4x9-hsotg" },
217 { .compatible = "st,stm32f7-hsotg",
219 { .compatible = "st,stm32mp15-fsotg",
221 { .compatible = "st,stm32mp15-hsotg",
231 switch (hsotg->hw_params.op_mode) { in dwc2_set_param_otg_cap()
245 hsotg->params.otg_cap = val; in dwc2_set_param_otg_cap()
251 u32 hs_phy_type = hsotg->hw_params.hs_phy_type; in dwc2_set_param_phy_type()
263 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS; in dwc2_set_param_phy_type()
265 hsotg->params.phy_type = val; in dwc2_set_param_phy_type()
272 val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ? in dwc2_set_param_speed()
281 hsotg->params.speed = val; in dwc2_set_param_speed()
288 val = (hsotg->hw_params.utmi_phy_data_width == in dwc2_set_param_phy_utmi_width()
291 if (hsotg->phy) { in dwc2_set_param_phy_utmi_width()
294 * width is 8-bit and set the phyif appropriately. in dwc2_set_param_phy_utmi_width()
296 if (phy_get_bus_width(hsotg->phy) == 8) in dwc2_set_param_phy_utmi_width()
300 hsotg->params.phy_utmi_width = val; in dwc2_set_param_phy_utmi_width()
305 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_param_tx_fifo_sizes()
312 memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size)); in dwc2_set_param_tx_fifo_sizes()
315 p->g_tx_fifo_size[i] = depth_average; in dwc2_set_param_tx_fifo_sizes()
322 if (hsotg->hw_params.hibernation) in dwc2_set_param_power_down()
324 else if (hsotg->hw_params.power_optimized) in dwc2_set_param_power_down()
329 hsotg->params.power_down = val; in dwc2_set_param_power_down()
334 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_param_lpm()
336 p->lpm = hsotg->hw_params.lpm_mode; in dwc2_set_param_lpm()
337 if (p->lpm) { in dwc2_set_param_lpm()
338 p->lpm_clock_gating = true; in dwc2_set_param_lpm()
339 p->besl = true; in dwc2_set_param_lpm()
340 p->hird_threshold_en = true; in dwc2_set_param_lpm()
341 p->hird_threshold = 4; in dwc2_set_param_lpm()
343 p->lpm_clock_gating = false; in dwc2_set_param_lpm()
344 p->besl = false; in dwc2_set_param_lpm()
345 p->hird_threshold_en = false; in dwc2_set_param_lpm()
350 * dwc2_set_default_params() - Set all core parameters to their
351 * auto-detected default values.
358 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_set_default_params()
359 struct dwc2_core_params *p = &hsotg->params; in dwc2_set_default_params()
360 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); in dwc2_set_default_params()
368 p->phy_ulpi_ddr = false; in dwc2_set_default_params()
369 p->phy_ulpi_ext_vbus = false; in dwc2_set_default_params()
371 p->enable_dynamic_fifo = hw->enable_dynamic_fifo; in dwc2_set_default_params()
372 p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo; in dwc2_set_default_params()
373 p->i2c_enable = hw->i2c_enable; in dwc2_set_default_params()
374 p->acg_enable = hw->acg_enable; in dwc2_set_default_params()
375 p->ulpi_fs_ls = false; in dwc2_set_default_params()
376 p->ts_dline = false; in dwc2_set_default_params()
377 p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a); in dwc2_set_default_params()
378 p->uframe_sched = true; in dwc2_set_default_params()
379 p->external_id_pin_ctl = false; in dwc2_set_default_params()
380 p->ipg_isoc_en = false; in dwc2_set_default_params()
381 p->service_interval = false; in dwc2_set_default_params()
382 p->max_packet_count = hw->max_packet_count; in dwc2_set_default_params()
383 p->max_transfer_size = hw->max_transfer_size; in dwc2_set_default_params()
384 p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT; in dwc2_set_default_params()
385 p->ref_clk_per = 33333; in dwc2_set_default_params()
386 p->sof_cnt_wkup_alert = 100; in dwc2_set_default_params()
388 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || in dwc2_set_default_params()
389 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_set_default_params()
390 p->host_dma = dma_capable; in dwc2_set_default_params()
391 p->dma_desc_enable = false; in dwc2_set_default_params()
392 p->dma_desc_fs_enable = false; in dwc2_set_default_params()
393 p->host_support_fs_ls_low_power = false; in dwc2_set_default_params()
394 p->host_ls_low_power_phy_clk = false; in dwc2_set_default_params()
395 p->host_channels = hw->host_channels; in dwc2_set_default_params()
396 p->host_rx_fifo_size = hw->rx_fifo_size; in dwc2_set_default_params()
397 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size; in dwc2_set_default_params()
398 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size; in dwc2_set_default_params()
401 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_set_default_params()
402 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_set_default_params()
403 p->g_dma = dma_capable; in dwc2_set_default_params()
404 p->g_dma_desc = hw->dma_desc_enable; in dwc2_set_default_params()
409 * gadget driver. These defaults have been hard-coded in dwc2_set_default_params()
412 * auto-detect if the hardware does not support the in dwc2_set_default_params()
415 p->g_rx_fifo_size = 2048; in dwc2_set_default_params()
416 p->g_np_tx_fifo_size = 1024; in dwc2_set_default_params()
422 * dwc2_get_device_properties() - Read in device properties.
430 struct dwc2_core_params *p = &hsotg->params; in dwc2_get_device_properties()
433 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_get_device_properties()
434 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_get_device_properties()
435 device_property_read_u32(hsotg->dev, "g-rx-fifo-size", in dwc2_get_device_properties()
436 &p->g_rx_fifo_size); in dwc2_get_device_properties()
438 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size", in dwc2_get_device_properties()
439 &p->g_np_tx_fifo_size); in dwc2_get_device_properties()
441 num = device_property_count_u32(hsotg->dev, "g-tx-fifo-size"); in dwc2_get_device_properties()
444 memset(p->g_tx_fifo_size, 0, in dwc2_get_device_properties()
445 sizeof(p->g_tx_fifo_size)); in dwc2_get_device_properties()
446 device_property_read_u32_array(hsotg->dev, in dwc2_get_device_properties()
447 "g-tx-fifo-size", in dwc2_get_device_properties()
448 &p->g_tx_fifo_size[1], in dwc2_get_device_properties()
453 if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL)) in dwc2_get_device_properties()
454 p->oc_disable = true; in dwc2_get_device_properties()
461 switch (hsotg->params.otg_cap) { in dwc2_check_param_otg_cap()
463 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) in dwc2_check_param_otg_cap()
467 switch (hsotg->hw_params.op_mode) { in dwc2_check_param_otg_cap()
496 hs_phy_type = hsotg->hw_params.hs_phy_type; in dwc2_check_param_phy_type()
497 fs_phy_type = hsotg->hw_params.fs_phy_type; in dwc2_check_param_phy_type()
499 switch (hsotg->params.phy_type) { in dwc2_check_param_phy_type()
525 int phy_type = hsotg->params.phy_type; in dwc2_check_param_speed()
526 int speed = hsotg->params.speed; in dwc2_check_param_speed()
530 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) && in dwc2_check_param_speed()
549 int param = hsotg->params.phy_utmi_width; in dwc2_check_param_phy_utmi_width()
550 int width = hsotg->hw_params.utmi_phy_data_width; in dwc2_check_param_phy_utmi_width()
570 int param = hsotg->params.power_down; in dwc2_check_param_power_down()
576 if (hsotg->hw_params.power_optimized) in dwc2_check_param_power_down()
578 dev_dbg(hsotg->dev, in dwc2_check_param_power_down()
583 if (hsotg->hw_params.hibernation) in dwc2_check_param_power_down()
585 dev_dbg(hsotg->dev, in dwc2_check_param_power_down()
590 dev_err(hsotg->dev, in dwc2_check_param_power_down()
597 hsotg->params.power_down = param; in dwc2_check_param_power_down()
609 min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4; in dwc2_check_param_tx_fifo_sizes()
612 total += hsotg->params.g_tx_fifo_size[fifo]; in dwc2_check_param_tx_fifo_sizes()
615 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n", in dwc2_check_param_tx_fifo_sizes()
621 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo]; in dwc2_check_param_tx_fifo_sizes()
623 if (hsotg->params.g_tx_fifo_size[fifo] < min || in dwc2_check_param_tx_fifo_sizes()
624 hsotg->params.g_tx_fifo_size[fifo] > dptxfszn) { in dwc2_check_param_tx_fifo_sizes()
625 dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n", in dwc2_check_param_tx_fifo_sizes()
627 hsotg->params.g_tx_fifo_size[fifo]); in dwc2_check_param_tx_fifo_sizes()
628 hsotg->params.g_tx_fifo_size[fifo] = dptxfszn; in dwc2_check_param_tx_fifo_sizes()
634 if ((int)(hsotg->params._param) < (_min) || \
635 (hsotg->params._param) > (_max)) { \
636 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
637 __func__, #_param, hsotg->params._param); \
638 hsotg->params._param = (_def); \
643 if (hsotg->params._param && !(_check)) { \
644 dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
645 __func__, #_param, hsotg->params._param); \
646 hsotg->params._param = false; \
652 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_check_params()
653 struct dwc2_core_params *p = &hsotg->params; in dwc2_check_params()
654 bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH); in dwc2_check_params()
661 CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo); in dwc2_check_params()
662 CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo); in dwc2_check_params()
663 CHECK_BOOL(i2c_enable, hw->i2c_enable); in dwc2_check_params()
664 CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en); in dwc2_check_params()
665 CHECK_BOOL(acg_enable, hw->acg_enable); in dwc2_check_params()
666 CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a)); in dwc2_check_params()
667 CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a)); in dwc2_check_params()
668 CHECK_BOOL(lpm, hw->lpm_mode); in dwc2_check_params()
669 CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm); in dwc2_check_params()
670 CHECK_BOOL(besl, hsotg->params.lpm); in dwc2_check_params()
671 CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)); in dwc2_check_params()
672 CHECK_BOOL(hird_threshold_en, hsotg->params.lpm); in dwc2_check_params()
673 CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0); in dwc2_check_params()
674 CHECK_BOOL(service_interval, hw->service_interval_mode); in dwc2_check_params()
676 15, hw->max_packet_count, in dwc2_check_params()
677 hw->max_packet_count); in dwc2_check_params()
679 2047, hw->max_transfer_size, in dwc2_check_params()
680 hw->max_transfer_size); in dwc2_check_params()
682 if ((hsotg->dr_mode == USB_DR_MODE_HOST) || in dwc2_check_params()
683 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_check_params()
685 CHECK_BOOL(dma_desc_enable, p->host_dma); in dwc2_check_params()
686 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable); in dwc2_check_params()
688 p->phy_type == DWC2_PHY_TYPE_PARAM_FS); in dwc2_check_params()
690 1, hw->host_channels, in dwc2_check_params()
691 hw->host_channels); in dwc2_check_params()
693 16, hw->rx_fifo_size, in dwc2_check_params()
694 hw->rx_fifo_size); in dwc2_check_params()
696 16, hw->host_nperio_tx_fifo_size, in dwc2_check_params()
697 hw->host_nperio_tx_fifo_size); in dwc2_check_params()
699 16, hw->host_perio_tx_fifo_size, in dwc2_check_params()
700 hw->host_perio_tx_fifo_size); in dwc2_check_params()
703 if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) || in dwc2_check_params()
704 (hsotg->dr_mode == USB_DR_MODE_OTG)) { in dwc2_check_params()
706 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable)); in dwc2_check_params()
708 16, hw->rx_fifo_size, in dwc2_check_params()
709 hw->rx_fifo_size); in dwc2_check_params()
711 16, hw->dev_nperio_tx_fifo_size, in dwc2_check_params()
712 hw->dev_nperio_tx_fifo_size); in dwc2_check_params()
724 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_host_hwparams()
728 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) in dwc2_get_host_hwparams()
736 hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_host_hwparams()
738 hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_host_hwparams()
749 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_dev_hwparams()
753 if (hsotg->dr_mode == USB_DR_MODE_HOST) in dwc2_get_dev_hwparams()
763 hw->g_tx_fifo_size[fifo] = in dwc2_get_dev_hwparams()
768 hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> in dwc2_get_dev_hwparams()
781 struct dwc2_hw_params *hw = &hsotg->hw_params; in dwc2_get_hwparams()
793 hw->dev_ep_dirs = hwcfg1; in dwc2_get_hwparams()
796 hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >> in dwc2_get_hwparams()
798 hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >> in dwc2_get_hwparams()
800 hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO); in dwc2_get_hwparams()
801 hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >> in dwc2_get_hwparams()
803 hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >> in dwc2_get_hwparams()
805 hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> in dwc2_get_hwparams()
807 hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >> in dwc2_get_hwparams()
809 hw->nperio_tx_q_depth = in dwc2_get_hwparams()
812 hw->host_perio_tx_q_depth = in dwc2_get_hwparams()
815 hw->dev_token_q_depth = in dwc2_get_hwparams()
822 hw->max_transfer_size = (1 << (width + 11)) - 1; in dwc2_get_hwparams()
825 hw->max_packet_count = (1 << (width + 4)) - 1; in dwc2_get_hwparams()
826 hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C); in dwc2_get_hwparams()
827 hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >> in dwc2_get_hwparams()
829 hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN); in dwc2_get_hwparams()
832 hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN); in dwc2_get_hwparams()
833 hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >> in dwc2_get_hwparams()
835 hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >> in dwc2_get_hwparams()
837 hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA); in dwc2_get_hwparams()
838 hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ); in dwc2_get_hwparams()
839 hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER); in dwc2_get_hwparams()
840 hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >> in dwc2_get_hwparams()
842 hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED); in dwc2_get_hwparams()
843 hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED); in dwc2_get_hwparams()
844 hw->service_interval_mode = !!(hwcfg4 & in dwc2_get_hwparams()
848 hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >> in dwc2_get_hwparams()
869 match = of_match_device(dwc2_of_match_table, hsotg->dev); in dwc2_init_params()
870 if (match && match->data) { in dwc2_init_params()
871 set_params = match->data; in dwc2_init_params()