71 	dev_dbg(hsotg->dev, "%s\n", __func__);  in dwc2_backup_global_registers()
103 	dev_dbg(hsotg->dev, "%s\n", __func__);  in dwc2_restore_global_registers()
263 	dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);  in dwc2_restore_essential_regs()
372 		dev_dbg(hsotg->dev,  in dwc2_hib_restore_common()
376 		dev_dbg(hsotg->dev, "restore done  generated here\n");  in dwc2_hib_restore_common()
594 	dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");  in dwc2_force_mode()
643 	dev_dbg(hsotg->dev, "Clearing force mode bits\n");  in dwc2_clear_force_mode()
690 		dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");  in dwc2_enable_acg()
710 	dev_dbg(hsotg->dev, "Host Global Registers\n");  in dwc2_dump_host_registers()
712 	dev_dbg(hsotg->dev, "HCFG	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
715 	dev_dbg(hsotg->dev, "HFIR	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
718 	dev_dbg(hsotg->dev, "HFNUM	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
721 	dev_dbg(hsotg->dev, "HPTXSTS	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
724 	dev_dbg(hsotg->dev, "HAINT	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
727 	dev_dbg(hsotg->dev, "HAINTMSK	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
731 		dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
736 	dev_dbg(hsotg->dev, "HPRT0	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
740 		dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);  in dwc2_dump_host_registers()
742 		dev_dbg(hsotg->dev, "HCCHAR	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
745 		dev_dbg(hsotg->dev, "HCSPLT	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
748 		dev_dbg(hsotg->dev, "HCINT	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
751 		dev_dbg(hsotg->dev, "HCINTMSK	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
754 		dev_dbg(hsotg->dev, "HCTSIZ	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
757 		dev_dbg(hsotg->dev, "HCDMA	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
761 			dev_dbg(hsotg->dev, "HCDMAB	 @0x%08lX : 0x%08X\n",  in dwc2_dump_host_registers()
782 	dev_dbg(hsotg->dev, "Core Global Registers\n");  in dwc2_dump_global_registers()
784 	dev_dbg(hsotg->dev, "GOTGCTL	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
787 	dev_dbg(hsotg->dev, "GOTGINT	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
790 	dev_dbg(hsotg->dev, "GAHBCFG	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
793 	dev_dbg(hsotg->dev, "GUSBCFG	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
796 	dev_dbg(hsotg->dev, "GRSTCTL	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
799 	dev_dbg(hsotg->dev, "GINTSTS	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
802 	dev_dbg(hsotg->dev, "GINTMSK	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
805 	dev_dbg(hsotg->dev, "GRXSTSR	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
808 	dev_dbg(hsotg->dev, "GRXFSIZ	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
811 	dev_dbg(hsotg->dev, "GNPTXFSIZ	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
814 	dev_dbg(hsotg->dev, "GNPTXSTS	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
817 	dev_dbg(hsotg->dev, "GI2CCTL	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
820 	dev_dbg(hsotg->dev, "GPVNDCTL	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
823 	dev_dbg(hsotg->dev, "GGPIO	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
826 	dev_dbg(hsotg->dev, "GUID	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
829 	dev_dbg(hsotg->dev, "GSNPSID	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
832 	dev_dbg(hsotg->dev, "GHWCFG1	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
835 	dev_dbg(hsotg->dev, "GHWCFG2	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
838 	dev_dbg(hsotg->dev, "GHWCFG3	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
841 	dev_dbg(hsotg->dev, "GHWCFG4	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
844 	dev_dbg(hsotg->dev, "GLPMCFG	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
847 	dev_dbg(hsotg->dev, "GPWRDN	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
850 	dev_dbg(hsotg->dev, "GDFIFOCFG	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
853 	dev_dbg(hsotg->dev, "HPTXFSIZ	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
857 	dev_dbg(hsotg->dev, "PCGCTL	 @0x%08lX : 0x%08X\n",  in dwc2_dump_global_registers()
1057 	dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);  in dwc2_init_fs_ls_pclk_sel()
1074 		dev_dbg(hsotg->dev, "FS PHY selected\n");  in dwc2_fs_phy_init()
1094 				dev_dbg(hsotg->dev, "Activating transceiver\n");  in dwc2_fs_phy_init()
1114 		dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");  in dwc2_fs_phy_init()
1153 		dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");  in dwc2_hs_phy_init()
1166 		dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");  in dwc2_hs_phy_init()
1222 		dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");  in dwc2_phy_init()