Lines Matching +full:cdns +full:- +full:pcie +full:- +full:host
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
17 * USBSS-DEV register interface.
22 * struct cdns3_usb_regs - device controller registers.
52 * @buf_addr: Address for On-chip Buffer operations.
53 * @buf_data: Data for On-chip Buffer operations.
54 * @buf_ctrl: On-chip Buffer Access Control.
122 /* USB_CONF - bitmasks */
131 /* Little Endian access - default */
145 /* DMA clock turn-off enable. */
147 /* DMA clock turn-off disable. */
189 /* USB_STS - bitmasks */
192 * 1 - device is in the configured state.
193 * 0 - device is not configured.
198 * On-chip memory overflow.
199 * 0 - On-chip memory status OK.
200 * 1 - On-chip memory overflow.
206 * 0 - USB in SuperSpeed mode disconnected.
207 * 1 - USB in SuperSpeed mode connected.
213 * 0 - single request.
214 * 1 - multiple TRB chain
221 * 0 - Undefined (value after reset).
222 * 1 - Low speed
223 * 2 - Full speed
224 * 3 - High speed
225 * 4 - Super speed
240 * 0 - Little Endian order (default after hardware reset).
241 * 1 - Big Endian order
246 * HS/FS clock turn-off status.
247 * 0 - hsfs clock is always on.
248 * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
254 * PCLK clock turn-off status.
255 * 0 - pclk clock is always on.
256 * 1 - pclk clock turn-off in U3 (SS mode) is enabled
263 * 0 - Internal reset is active.
264 * 1 - Internal reset is not active and controller is fully operational.
270 * 0 - disabled
271 * 1 - enabled
277 * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
278 * 1 - USB device is enabled (VBUS input is connected to the internal logic).
284 * 0 - USB device is default state.
285 * 1 - USB device is at least in address state.
291 * 0 - Entering to L1 LPM state disabled.
292 * 1 - Entering to L1 LPM state enabled.
298 * 0 - internal VBUS is not detected.
299 * 1 - internal VBUS is detected.
305 * 0 - L0 State
306 * 1 - L1 State
307 * 2 - L2 State
308 * 3 - L3 State
317 * 0 - the disconnect bit for HS/FS mode is set .
318 * 1 - the disconnect bit for HS/FS mode is not set.
324 * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
325 * 1 - High Speed operations in USB2.0 (FS/HS).
331 * 0 - Entering to U1 state disabled.
332 * 1 - Entering to U1 state enabled.
338 * 0 - Entering to U2 state disabled.
339 * 1 - Entering to U2 state enabled.
344 * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
361 * DMA clock turn-off status.
362 * 0 - DMA clock is always on (default after hardware reset).
363 * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
369 * 0 - Little Endian order (default after hardware reset).
370 * 1 - Big Endian order.
375 /* USB_CMD - bitmasks */
401 /*Device Notification 'Function Wake' - Interface value (only in SS mode. */
405 * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
411 /* USB_ITPN - bitmasks */
414 * In SS mode this field represent number of last ITP received from host.
415 * In HS/FS mode this field represent number of last SOF received from host.
420 /* USB_LPM - bitmasks */
421 /* Host Initiated Resume Duration. */
427 /* USB_IEN - bitmasks */
480 /* USB_ISTS - bitmasks */
528 /* USB_SEL - bitmasks */
532 /* Endpoint direction bit - 0 - OUT, 1 - IN. */
538 /* EP_TRADDR - bitmasks */
542 /* EP_CFG - bitmasks */
547 * 1 - isochronous
548 * 2 - bulk
549 * 3 - interrupt
574 /* EP_CMD - bitmasks */
608 /* EP_STS - bitmasks */
641 /* Host Packet Pending (only for SS mode). */
660 /* EP_STS_SID - bitmasks */
665 /* EP_STS_EN - bitmasks */
691 /* DRBL- bitmasks */
696 /* EP_IEN - bitmasks */
701 /* EP_ISTS - bitmasks */
706 /* USB_PWR- bitmasks */
712 * Enables turning-off Reference Clock.
727 /* USB_CONF2- bitmasks */
741 /* USB_CAP1- bitmasks */
745 * 0x0 - OCP
746 * 0x1 - AHB,
747 * 0x2 - PLB
748 * 0x3 - AXI
749 * 0x4-0xF - reserved
759 * 0x0 - 8 bit interface,
760 * 0x1 - 16 bit interface,
761 * 0x2 - 32 bit interface
762 * 0x3 - 64 bit interface
763 * 0x4-0xF - reserved
773 * 0x0 - OCP
774 * 0x1 - AHB,
775 * 0x2 - PLB
776 * 0x3 - AXI
777 * 0x4-0xF - reserved
787 * 0x0 - reserved,
788 * 0x1 - reserved,
789 * 0x2 - 32 bit interface
790 * 0x3 - 64 bit interface
791 * 0x4-0xF - reserved
799 * 0x0 - USB PIPE,
800 * 0x1 - RMMI,
801 * 0x2-0xF - reserved
809 * 0x0 - 8 bit PIPE interface,
810 * 0x1 - 16 bit PIPE interface,
811 * 0x2 - 32 bit PIPE interface,
812 * 0x3 - 64 bit PIPE interface
813 * 0x4-0xF - reserved
830 * 0x0 - interface NOT implemented,
831 * 0x1 - interface implemented
837 * 0x0 - UTMI,
838 * 0x1 - ULPI
844 * 0x0 - 8 bit interface,
845 * 0x1 - 16 bit interface,
851 * 0x0 - pure device mode
852 * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
863 /* USB_CAP2- bitmasks */
865 * The actual size of the connected On-chip RAM memory in kB:
866 * - 0 means 256 kB (max supported mem size)
867 * - value other than 0 reflects the mem size in kB
872 * These field reflects width of on-chip RAM address bus width,
874 * 0x0-0x7 - reserved,
875 * 0x8 - support for 4kB mem,
876 * 0x9 - support for 8kB mem,
877 * 0xA - support for 16kB mem,
878 * 0xB - support for 32kB mem,
879 * 0xC - support for 64kB mem,
880 * 0xD - support for 128kB mem,
881 * 0xE - support for 256kB mem,
882 * 0xF - reserved
886 /* USB_CAP3- bitmasks */
889 /* USB_CAP4- bitmasks */
892 /* USB_CAP5- bitmasks */
895 /* USB_CAP6- bitmasks */
896 /* The USBSS-DEV Controller Internal build number. */
898 /* The USBSS-DEV Controller version number. */
906 /* DBG_LINK1- bitmasks */
919 * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
923 * 1: USBSS_DEV will not terminate Far-end receiver termination
954 /* DMA_AXI_CTRL- bitmasks */
965 /*-------------------------------------------------------------------------*/
967 * USBSS-DEV DMA interface.
986 *Only for ISOC endpoints - maximum number of TRBs is calculated as
987 * pow(2, bInterval-1) * number of usb requests. It is limitation made by
997 * struct cdns3_trb - represent Transfer Descriptor block.
1027 /* Cycle bit - indicates TRB ownership by driver or hw*/
1043 * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
1044 * - Shall be set to 1 by Controller when Short Packet condition for this TRB
1053 /* Set PCIe no snoop attribute */
1074 /* transfer_len bitmasks - bits 31:24 */
1081 /*-------------------------------------------------------------------------*/
1102 /*-------------------------------------------------------------------------*/
1108 * struct cdns3_endpoint - extended device side representation of USB endpoint.
1113 * @trb_pool: transfer ring - array of transaction buffers
1118 * @descmis_req: internal transfer object used for getting data from on-chip
1122 * @num: endpoint number (1 - 15)
1196 * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
1213 * struct cdns3_request - extended device side representation of usb_request
1253 * struct cdns3_device - represent USB device.
1263 * @zlp_buf - zlp buffer
1277 * @wake_up_flag: allow device to remote up the host
1280 * @onchip_buffers: number of available on-chip buffers.
1281 * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
1296 /* generic spin-lock for drivers */