Lines Matching refs:TCR
394 #define TCR 0x82 /* tx control */ macro
1385 value = rd_reg16(info, TCR); in set_break()
1390 wr_reg16(info, TCR, value); in set_break()
2265 unsigned short val = rd_reg16(info, TCR); in isr_txeom()
2266 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in isr_txeom()
2267 wr_reg16(info, TCR, val); /* clear reset bit */ in isr_txeom()
2850 val = rd_reg16(info, TCR); in set_interface()
2855 wr_reg16(info, TCR, val); in set_interface()
4011 wr_reg16(info, TCR, in tx_start()
4012 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); in tx_start()
4055 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */ in tx_stop()
4056 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ in tx_stop()
4142 wr_reg16(info, TCR, val); in async_mode()
4304 wr_reg16(info, TCR, val); in sync_mode()
4466 tcr = rd_reg16(info, TCR); in tx_set_idle()
4476 wr_reg16(info, TCR, tcr); in tx_set_idle()
4965 wr_reg16(info, TCR, in irq_test()
4966 (unsigned short)(rd_reg16(info, TCR) | BIT1)); in irq_test()