Lines Matching refs:usc_OutReg
515 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
553 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF))…
573 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
574 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
606 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
609 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
612 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
615 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
617 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
644 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
647 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
659 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
661 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
668 static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
673 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
674 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
676 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
1175 usc_OutReg(info, CMR, info->cmr_value); in mgsl_isr_receive_status()
1178 usc_OutReg(info, RICR, in mgsl_isr_receive_status()
1383 usc_OutReg( info, SICR, in mgsl_isr_io_pin()
1449 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 )); in mgsl_isr_receive_data()
1838 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14)); in shutdown()
1843 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12)); in shutdown()
2700 usc_OutReg(info, RICR, newreg); in mgsl_wait_event()
2763 usc_OutReg(info, RICR, usc_InReg(info,RICR) & in mgsl_wait_event()
2899 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7)); in mgsl_break()
2901 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7)); in mgsl_break()
4435 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue ) in usc_OutReg() function
4487 usc_OutReg(info,TMCR,0x1f); in usc_set_sdlc_mode()
4528 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */ in usc_set_sdlc_mode()
4568 usc_OutReg( info, RSR, info->params.addr_filter ); in usc_set_sdlc_mode()
4572 usc_OutReg( info, CMR, RegValue ); in usc_set_sdlc_mode()
4607 usc_OutReg( info, RMR, RegValue ); in usc_set_sdlc_mode()
4616 usc_OutReg( info, RCLR, RCLRVALUE ); in usc_set_sdlc_mode()
4640 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) ); in usc_set_sdlc_mode()
4679 usc_OutReg( info, TMR, RegValue ); in usc_set_sdlc_mode()
4701 usc_OutReg( info, TICR, 0x0736 ); in usc_set_sdlc_mode()
4728 usc_OutReg( info, TCSR, info->tcsr_value ); in usc_set_sdlc_mode()
4763 usc_OutReg( info, CMCR, RegValue ); in usc_set_sdlc_mode()
4830 usc_OutReg( info, TC1R, Tc ); in usc_set_sdlc_mode()
4846 usc_OutReg( info, HCR, RegValue ); in usc_set_sdlc_mode()
4867 usc_OutReg( info, CCSR, 0x1020 ); in usc_set_sdlc_mode()
4871 usc_OutReg( info, SICR, in usc_set_sdlc_mode()
4883 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3)); in usc_set_sdlc_mode()
4997 usc_OutReg( info, CCR, RegValue ); in usc_set_sdlc_mode()
5029 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6)); in usc_enable_loopback()
5044 usc_OutReg( info, CMCR, 0x0f64 ); in usc_enable_loopback()
5049 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1)); in usc_enable_loopback()
5051 usc_OutReg(info, TC0R, (u16)8); in usc_enable_loopback()
5055 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_loopback()
5058 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004)); in usc_enable_loopback()
5065 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6)); in usc_enable_loopback()
5107 usc_OutReg( info, TC0R, Tc ); in usc_enable_aux_clock()
5115 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_aux_clock()
5118 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) ); in usc_enable_aux_clock()
5121 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); in usc_enable_aux_clock()
5241 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); in usc_process_rxoverrun_sync()
5266 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); in usc_process_rxoverrun_sync()
5296 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); in usc_stop_receiver()
5323 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); in usc_start_receiver()
5362 usc_OutReg( info, CCSR, 0x1020 ); in usc_start_receiver()
5428 usc_OutReg( info, TCLR, (u16)FrameSize ); in usc_start_transmitter()
5648 usc_OutReg( info, PCR, 0xf0f5 ); in usc_reset()
5665 usc_OutReg( info, IOCR, 0x0004 ); in usc_reset()
5703 usc_OutReg( info, CMR, RegValue ); in usc_set_async_mode()
5729 usc_OutReg( info, RMR, RegValue ); in usc_set_async_mode()
5757 usc_OutReg( info, RICR, 0x0000 ); in usc_set_async_mode()
5786 usc_OutReg( info, TMR, RegValue ); in usc_set_async_mode()
5811 usc_OutReg( info, TICR, 0x1f40 ); in usc_set_async_mode()
5837 usc_OutReg( info, CCSR, 0x0020 ); in usc_set_async_mode()
5881 usc_OutReg( info, TC0R, 0 ); in usc_loopback_frame()
5897 usc_OutReg( info, CCR, 0x0100 ); in usc_loopback_frame()
5906 usc_OutReg( info, TCLR, 2 ); in usc_loopback_frame()
5973 usc_OutReg(info, TCSR, info->tcsr_value); in usc_set_txidle()
6071 usc_OutReg( info, PCR, Control ); in usc_set_serial_signals()
6101 usc_OutReg( info, CMCR, 0x0f64 ); in usc_enable_async_clock()
6110 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) ); in usc_enable_async_clock()
6118 usc_OutReg( info, HCR, in usc_enable_async_clock()
6124 usc_OutReg( info, IOCR, in usc_enable_async_clock()
6128 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); in usc_enable_async_clock()
6764 usc_OutReg( info, TC0R, BitPatterns[i] ); in mgsl_register_test()
6765 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] ); in mgsl_register_test()
6766 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] ); in mgsl_register_test()
6767 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] ); in mgsl_register_test()
6768 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] ); in mgsl_register_test()
6814 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) ); in mgsl_irq_test()
6953 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) ); in mgsl_dma_test()
6993 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count ); in mgsl_dma_test()
7004 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) ); in mgsl_dma_test()
7051 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) ); in mgsl_dma_test()
7380 usc_OutReg(info, CMR, info->cmr_value); in usc_loopmode_send_done()
7404 usc_OutReg( info, RICR, in usc_loopmode_insert_request()
7409 usc_OutReg(info, CMR, info->cmr_value); in usc_loopmode_insert_request()