Lines Matching +full:dcd +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
8 * Inspired by st-asc.c from STMicroelectronics (c)
14 #include <linux/dma-direction.h>
16 #include <linux/dma-mapping.h>
35 #include "stm32-usart.h"
49 val = readl_relaxed(port->membase + reg); in stm32_set_bits()
51 writel_relaxed(val, port->membase + reg); in stm32_set_bits()
58 val = readl_relaxed(port->membase + reg); in stm32_clr_bits()
60 writel_relaxed(val, port->membase + reg); in stm32_clr_bits()
102 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_config_rs485()
103 struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_config_rs485()
107 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_config_rs485()
109 port->rs485 = *rs485conf; in stm32_config_rs485()
111 rs485conf->flags |= SER_RS485_RX_DURING_TX; in stm32_config_rs485()
113 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_config_rs485()
114 cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_config_rs485()
115 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_config_rs485()
116 usartdiv = readl_relaxed(port->membase + ofs->brr); in stm32_config_rs485()
124 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); in stm32_config_rs485()
126 rs485conf->delay_rts_before_send, in stm32_config_rs485()
127 rs485conf->delay_rts_after_send, baud); in stm32_config_rs485()
129 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_config_rs485()
131 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_config_rs485()
134 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_config_rs485()
137 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_config_rs485()
138 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_config_rs485()
140 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP); in stm32_config_rs485()
141 stm32_clr_bits(port, ofs->cr1, in stm32_config_rs485()
145 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_config_rs485()
153 struct serial_rs485 *rs485conf = &port->rs485; in stm32_init_rs485()
155 rs485conf->flags = 0; in stm32_init_rs485()
156 rs485conf->delay_rts_before_send = 0; in stm32_init_rs485()
157 rs485conf->delay_rts_after_send = 0; in stm32_init_rs485()
159 if (!pdev->dev.of_node) in stm32_init_rs485()
160 return -ENODEV; in stm32_init_rs485()
169 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_pending_rx()
173 *sr = readl_relaxed(port->membase + ofs->isr); in stm32_pending_rx()
175 if (threaded && stm32_port->rx_ch) { in stm32_pending_rx()
176 status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_pending_rx()
177 stm32_port->rx_ch->cookie, in stm32_pending_rx()
194 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_get_char()
197 if (stm32_port->rx_ch) { in stm32_get_char()
198 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--]; in stm32_get_char()
202 c = readl_relaxed(port->membase + ofs->rdr); in stm32_get_char()
204 c &= stm32_port->rdr_mask; in stm32_get_char()
212 struct tty_port *tport = &port->state->port; in stm32_receive_chars()
214 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_receive_chars()
219 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) in stm32_receive_chars()
220 pm_wakeup_event(tport->tty->dev, 0); in stm32_receive_chars()
222 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) { in stm32_receive_chars()
235 * cleared by the sequence [read SR - read DR]. in stm32_receive_chars()
237 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) in stm32_receive_chars()
239 port->membase + ofs->icr); in stm32_receive_chars()
241 c = stm32_get_char(port, &sr, &stm32_port->last_res); in stm32_receive_chars()
242 port->icount.rx++; in stm32_receive_chars()
245 port->icount.overrun++; in stm32_receive_chars()
247 port->icount.parity++; in stm32_receive_chars()
251 port->icount.brk++; in stm32_receive_chars()
255 port->icount.frame++; in stm32_receive_chars()
259 sr &= port->read_status_mask; in stm32_receive_chars()
276 spin_unlock(&port->lock); in stm32_receive_chars()
278 spin_lock(&port->lock); in stm32_receive_chars()
285 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_tx_dma_complete()
287 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_tx_dma_complete()
288 stm32port->tx_dma_busy = false; in stm32_tx_dma_complete()
297 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_tx_interrupt_enable()
303 if (stm32_port->fifoen) in stm32_tx_interrupt_enable()
304 stm32_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_tx_interrupt_enable()
306 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_tx_interrupt_enable()
312 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_tx_interrupt_disable()
314 if (stm32_port->fifoen) in stm32_tx_interrupt_disable()
315 stm32_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_tx_interrupt_disable()
317 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_tx_interrupt_disable()
323 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_transmit_chars_pio()
324 struct circ_buf *xmit = &port->state->xmit; in stm32_transmit_chars_pio()
326 if (stm32_port->tx_dma_busy) { in stm32_transmit_chars_pio()
327 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_transmit_chars_pio()
328 stm32_port->tx_dma_busy = false; in stm32_transmit_chars_pio()
333 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_transmit_chars_pio()
335 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); in stm32_transmit_chars_pio()
336 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in stm32_transmit_chars_pio()
337 port->icount.tx++; in stm32_transmit_chars_pio()
350 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_transmit_chars_dma()
351 struct circ_buf *xmit = &port->state->xmit; in stm32_transmit_chars_dma()
356 if (stm32port->tx_dma_busy) in stm32_transmit_chars_dma()
359 stm32port->tx_dma_busy = true; in stm32_transmit_chars_dma()
366 if (xmit->tail < xmit->head) { in stm32_transmit_chars_dma()
367 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); in stm32_transmit_chars_dma()
369 size_t one = UART_XMIT_SIZE - xmit->tail; in stm32_transmit_chars_dma()
374 two = count - one; in stm32_transmit_chars_dma()
376 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); in stm32_transmit_chars_dma()
378 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); in stm32_transmit_chars_dma()
381 desc = dmaengine_prep_slave_single(stm32port->tx_ch, in stm32_transmit_chars_dma()
382 stm32port->tx_dma_buf, in stm32_transmit_chars_dma()
388 for (i = count; i > 0; i--) in stm32_transmit_chars_dma()
393 desc->callback = stm32_tx_dma_complete; in stm32_transmit_chars_dma()
394 desc->callback_param = port; in stm32_transmit_chars_dma()
400 dma_async_issue_pending(stm32port->tx_ch); in stm32_transmit_chars_dma()
402 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_transmit_chars_dma()
404 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); in stm32_transmit_chars_dma()
405 port->icount.tx += count; in stm32_transmit_chars_dma()
411 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_transmit_chars()
412 struct circ_buf *xmit = &port->state->xmit; in stm32_transmit_chars()
414 if (port->x_char) { in stm32_transmit_chars()
415 if (stm32_port->tx_dma_busy) in stm32_transmit_chars()
416 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_transmit_chars()
417 writel_relaxed(port->x_char, port->membase + ofs->tdr); in stm32_transmit_chars()
418 port->x_char = 0; in stm32_transmit_chars()
419 port->icount.tx++; in stm32_transmit_chars()
420 if (stm32_port->tx_dma_busy) in stm32_transmit_chars()
421 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_transmit_chars()
430 if (ofs->icr == UNDEF_REG) in stm32_transmit_chars()
431 stm32_clr_bits(port, ofs->isr, USART_SR_TC); in stm32_transmit_chars()
433 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); in stm32_transmit_chars()
435 if (stm32_port->tx_ch) in stm32_transmit_chars()
451 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_interrupt()
454 spin_lock(&port->lock); in stm32_interrupt()
456 sr = readl_relaxed(port->membase + ofs->isr); in stm32_interrupt()
458 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) in stm32_interrupt()
460 port->membase + ofs->icr); in stm32_interrupt()
462 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG)) in stm32_interrupt()
464 port->membase + ofs->icr); in stm32_interrupt()
466 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch)) in stm32_interrupt()
469 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) in stm32_interrupt()
472 spin_unlock(&port->lock); in stm32_interrupt()
474 if (stm32_port->rx_ch) in stm32_interrupt()
485 spin_lock(&port->lock); in stm32_threaded_interrupt()
487 if (stm32_port->rx_ch) in stm32_threaded_interrupt()
490 spin_unlock(&port->lock); in stm32_threaded_interrupt()
498 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_tx_empty()
500 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE; in stm32_tx_empty()
506 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_set_mctrl()
508 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) in stm32_set_mctrl()
509 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_set_mctrl()
511 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_set_mctrl()
513 mctrl_gpio_set(stm32_port->gpios, mctrl); in stm32_set_mctrl()
521 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */ in stm32_get_mctrl()
524 return mctrl_gpio_get(stm32_port->gpios, &ret); in stm32_get_mctrl()
529 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); in stm32_enable_ms()
534 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); in stm32_disable_ms()
541 struct serial_rs485 *rs485conf = &port->rs485; in stm32_stop_tx()
545 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_stop_tx()
546 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_stop_tx()
547 mctrl_gpio_set(stm32_port->gpios, in stm32_stop_tx()
548 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_stop_tx()
550 mctrl_gpio_set(stm32_port->gpios, in stm32_stop_tx()
551 stm32_port->port.mctrl | TIOCM_RTS); in stm32_stop_tx()
560 struct serial_rs485 *rs485conf = &port->rs485; in stm32_start_tx()
561 struct circ_buf *xmit = &port->state->xmit; in stm32_start_tx()
566 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_start_tx()
567 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_start_tx()
568 mctrl_gpio_set(stm32_port->gpios, in stm32_start_tx()
569 stm32_port->port.mctrl | TIOCM_RTS); in stm32_start_tx()
571 mctrl_gpio_set(stm32_port->gpios, in stm32_start_tx()
572 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_start_tx()
583 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_throttle()
586 spin_lock_irqsave(&port->lock, flags); in stm32_throttle()
587 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_throttle()
588 if (stm32_port->cr3_irq) in stm32_throttle()
589 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_throttle()
591 spin_unlock_irqrestore(&port->lock, flags); in stm32_throttle()
598 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_unthrottle()
601 spin_lock_irqsave(&port->lock, flags); in stm32_unthrottle()
602 stm32_set_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_unthrottle()
603 if (stm32_port->cr3_irq) in stm32_unthrottle()
604 stm32_set_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_unthrottle()
606 spin_unlock_irqrestore(&port->lock, flags); in stm32_unthrottle()
613 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_stop_rx()
615 stm32_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_stop_rx()
616 if (stm32_port->cr3_irq) in stm32_stop_rx()
617 stm32_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_stop_rx()
621 /* Handle breaks - ignored by us */
629 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_startup()
630 const char *name = to_platform_device(port->dev)->name; in stm32_startup()
634 ret = request_threaded_irq(port->irq, stm32_interrupt, in stm32_startup()
641 if (ofs->rqr != UNDEF_REG) in stm32_startup()
642 stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); in stm32_startup()
645 if (stm32_port->fifoen) { in stm32_startup()
646 val = readl_relaxed(port->membase + ofs->cr3); in stm32_startup()
650 writel_relaxed(val, port->membase + ofs->cr3); in stm32_startup()
654 val = stm32_port->cr1_irq | USART_CR1_RE; in stm32_startup()
655 if (stm32_port->fifoen) in stm32_startup()
657 stm32_set_bits(port, ofs->cr1, val); in stm32_startup()
665 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_shutdown()
666 struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_shutdown()
674 val |= stm32_port->cr1_irq | USART_CR1_RE; in stm32_shutdown()
675 val |= BIT(cfg->uart_enable_bit); in stm32_shutdown()
676 if (stm32_port->fifoen) in stm32_shutdown()
679 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, in stm32_shutdown()
684 dev_err(port->dev, "transmission complete not set\n"); in stm32_shutdown()
686 stm32_clr_bits(port, ofs->cr1, val); in stm32_shutdown()
688 free_irq(port->irq, port); in stm32_shutdown()
695 tcflag_t cflag = termios->c_cflag; in stm32_get_databits()
725 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_set_termios()
726 struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_set_termios()
727 struct serial_rs485 *rs485conf = &port->rs485; in stm32_set_termios()
730 tcflag_t cflag = termios->c_cflag; in stm32_set_termios()
734 if (!stm32_port->hw_flow_control) in stm32_set_termios()
737 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); in stm32_set_termios()
739 spin_lock_irqsave(&port->lock, flags); in stm32_set_termios()
742 writel_relaxed(0, port->membase + ofs->cr1); in stm32_set_termios()
745 if (ofs->rqr != UNDEF_REG) in stm32_set_termios()
746 stm32_set_bits(port, ofs->rqr, in stm32_set_termios()
750 if (stm32_port->fifoen) in stm32_set_termios()
753 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_set_termios()
761 stm32_port->rdr_mask = (BIT(bits) - 1); in stm32_set_termios()
777 else if ((bits == 7) && cfg->has_7bits_data) in stm32_set_termios()
780 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" in stm32_set_termios()
783 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || in stm32_set_termios()
784 stm32_port->fifoen)) { in stm32_set_termios()
791 stm32_port->cr1_irq = USART_CR1_RTOIE; in stm32_set_termios()
792 writel_relaxed(bits, port->membase + ofs->rtor); in stm32_set_termios()
795 if (!stm32_port->rx_ch) in stm32_set_termios()
796 stm32_port->cr3_irq = USART_CR3_RXFTIE; in stm32_set_termios()
799 cr1 |= stm32_port->cr1_irq; in stm32_set_termios()
800 cr3 |= stm32_port->cr3_irq; in stm32_set_termios()
805 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in stm32_set_termios()
807 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in stm32_set_termios()
812 if (UART_ENABLE_MS(port, termios->c_cflag)) in stm32_set_termios()
817 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); in stm32_set_termios()
828 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_set_termios()
832 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_set_termios()
837 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); in stm32_set_termios()
841 port->read_status_mask = USART_SR_ORE; in stm32_set_termios()
842 if (termios->c_iflag & INPCK) in stm32_set_termios()
843 port->read_status_mask |= USART_SR_PE | USART_SR_FE; in stm32_set_termios()
844 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in stm32_set_termios()
845 port->read_status_mask |= USART_SR_FE; in stm32_set_termios()
848 port->ignore_status_mask = 0; in stm32_set_termios()
849 if (termios->c_iflag & IGNPAR) in stm32_set_termios()
850 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; in stm32_set_termios()
851 if (termios->c_iflag & IGNBRK) { in stm32_set_termios()
852 port->ignore_status_mask |= USART_SR_FE; in stm32_set_termios()
857 if (termios->c_iflag & IGNPAR) in stm32_set_termios()
858 port->ignore_status_mask |= USART_SR_ORE; in stm32_set_termios()
862 if ((termios->c_cflag & CREAD) == 0) in stm32_set_termios()
863 port->ignore_status_mask |= USART_SR_DUMMY_RX; in stm32_set_termios()
865 if (stm32_port->rx_ch) in stm32_set_termios()
868 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_set_termios()
870 rs485conf->delay_rts_before_send, in stm32_set_termios()
871 rs485conf->delay_rts_after_send, baud); in stm32_set_termios()
872 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_set_termios()
874 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_set_termios()
877 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_set_termios()
885 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_set_termios()
886 writel_relaxed(cr2, port->membase + ofs->cr2); in stm32_set_termios()
887 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_set_termios()
889 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_set_termios()
890 spin_unlock_irqrestore(&port->lock, flags); in stm32_set_termios()
895 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; in stm32_type()
910 port->type = PORT_STM32; in stm32_config_port()
917 return -EINVAL; in stm32_verify_port()
925 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_pm()
926 struct stm32_usart_config *cfg = &stm32port->info->cfg; in stm32_pm()
931 pm_runtime_get_sync(port->dev); in stm32_pm()
934 spin_lock_irqsave(&port->lock, flags); in stm32_pm()
935 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_pm()
936 spin_unlock_irqrestore(&port->lock, flags); in stm32_pm()
937 pm_runtime_put_sync(port->dev); in stm32_pm()
967 struct uart_port *port = &stm32port->port; in stm32_init_port()
971 port->iotype = UPIO_MEM; in stm32_init_port()
972 port->flags = UPF_BOOT_AUTOCONF; in stm32_init_port()
973 port->ops = &stm32_uart_ops; in stm32_init_port()
974 port->dev = &pdev->dev; in stm32_init_port()
975 port->fifosize = stm32port->info->cfg.fifosize; in stm32_init_port()
976 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); in stm32_init_port()
980 return ret ? : -ENODEV; in stm32_init_port()
981 port->irq = ret; in stm32_init_port()
983 port->rs485_config = stm32_config_rs485; in stm32_init_port()
989 if (stm32port->info->cfg.has_wakeup) { in stm32_init_port()
990 stm32port->wakeirq = platform_get_irq_optional(pdev, 1); in stm32_init_port()
991 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) in stm32_init_port()
992 return stm32port->wakeirq ? : -ENODEV; in stm32_init_port()
995 stm32port->fifoen = stm32port->info->cfg.has_fifo; in stm32_init_port()
998 port->membase = devm_ioremap_resource(&pdev->dev, res); in stm32_init_port()
999 if (IS_ERR(port->membase)) in stm32_init_port()
1000 return PTR_ERR(port->membase); in stm32_init_port()
1001 port->mapbase = res->start; in stm32_init_port()
1003 spin_lock_init(&port->lock); in stm32_init_port()
1005 stm32port->clk = devm_clk_get(&pdev->dev, NULL); in stm32_init_port()
1006 if (IS_ERR(stm32port->clk)) in stm32_init_port()
1007 return PTR_ERR(stm32port->clk); in stm32_init_port()
1010 ret = clk_prepare_enable(stm32port->clk); in stm32_init_port()
1014 stm32port->port.uartclk = clk_get_rate(stm32port->clk); in stm32_init_port()
1015 if (!stm32port->port.uartclk) { in stm32_init_port()
1016 ret = -EINVAL; in stm32_init_port()
1020 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); in stm32_init_port()
1021 if (IS_ERR(stm32port->gpios)) { in stm32_init_port()
1022 ret = PTR_ERR(stm32port->gpios); in stm32_init_port()
1026 /* Both CTS/RTS gpios and "st,hw-flow-ctrl" should not be specified */ in stm32_init_port()
1027 if (stm32port->hw_flow_control) { in stm32_init_port()
1028 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || in stm32_init_port()
1029 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { in stm32_init_port()
1030 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); in stm32_init_port()
1031 ret = -EINVAL; in stm32_init_port()
1039 clk_disable_unprepare(stm32port->clk); in stm32_init_port()
1046 struct device_node *np = pdev->dev.of_node; in stm32_of_get_stm32_port()
1054 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); in stm32_of_get_stm32_port()
1062 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || in stm32_of_get_stm32_port()
1063 of_property_read_bool (np, "uart-has-rtscts"); in stm32_of_get_stm32_port()
1073 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1074 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1075 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1085 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_of_dma_rx_probe()
1086 struct uart_port *port = &stm32port->port; in stm32_of_dma_rx_probe()
1087 struct device *dev = &pdev->dev; in stm32_of_dma_rx_probe()
1094 stm32port->rx_ch = dma_request_slave_channel(dev, "rx"); in stm32_of_dma_rx_probe()
1095 if (!stm32port->rx_ch) { in stm32_of_dma_rx_probe()
1097 return -ENODEV; in stm32_of_dma_rx_probe()
1099 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L, in stm32_of_dma_rx_probe()
1100 &stm32port->rx_dma_buf, in stm32_of_dma_rx_probe()
1102 if (!stm32port->rx_buf) { in stm32_of_dma_rx_probe()
1103 ret = -ENOMEM; in stm32_of_dma_rx_probe()
1109 config.src_addr = port->mapbase + ofs->rdr; in stm32_of_dma_rx_probe()
1112 ret = dmaengine_slave_config(stm32port->rx_ch, &config); in stm32_of_dma_rx_probe()
1115 ret = -ENODEV; in stm32_of_dma_rx_probe()
1120 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch, in stm32_of_dma_rx_probe()
1121 stm32port->rx_dma_buf, in stm32_of_dma_rx_probe()
1126 ret = -ENODEV; in stm32_of_dma_rx_probe()
1131 desc->callback = NULL; in stm32_of_dma_rx_probe()
1132 desc->callback_param = NULL; in stm32_of_dma_rx_probe()
1138 dma_async_issue_pending(stm32port->rx_ch); in stm32_of_dma_rx_probe()
1143 dma_free_coherent(&pdev->dev, in stm32_of_dma_rx_probe()
1144 RX_BUF_L, stm32port->rx_buf, in stm32_of_dma_rx_probe()
1145 stm32port->rx_dma_buf); in stm32_of_dma_rx_probe()
1148 dma_release_channel(stm32port->rx_ch); in stm32_of_dma_rx_probe()
1149 stm32port->rx_ch = NULL; in stm32_of_dma_rx_probe()
1157 struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_of_dma_tx_probe()
1158 struct uart_port *port = &stm32port->port; in stm32_of_dma_tx_probe()
1159 struct device *dev = &pdev->dev; in stm32_of_dma_tx_probe()
1163 stm32port->tx_dma_busy = false; in stm32_of_dma_tx_probe()
1166 stm32port->tx_ch = dma_request_slave_channel(dev, "tx"); in stm32_of_dma_tx_probe()
1167 if (!stm32port->tx_ch) { in stm32_of_dma_tx_probe()
1169 return -ENODEV; in stm32_of_dma_tx_probe()
1171 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L, in stm32_of_dma_tx_probe()
1172 &stm32port->tx_dma_buf, in stm32_of_dma_tx_probe()
1174 if (!stm32port->tx_buf) { in stm32_of_dma_tx_probe()
1175 ret = -ENOMEM; in stm32_of_dma_tx_probe()
1181 config.dst_addr = port->mapbase + ofs->tdr; in stm32_of_dma_tx_probe()
1184 ret = dmaengine_slave_config(stm32port->tx_ch, &config); in stm32_of_dma_tx_probe()
1187 ret = -ENODEV; in stm32_of_dma_tx_probe()
1194 dma_free_coherent(&pdev->dev, in stm32_of_dma_tx_probe()
1195 TX_BUF_L, stm32port->tx_buf, in stm32_of_dma_tx_probe()
1196 stm32port->tx_dma_buf); in stm32_of_dma_tx_probe()
1199 dma_release_channel(stm32port->tx_ch); in stm32_of_dma_tx_probe()
1200 stm32port->tx_ch = NULL; in stm32_of_dma_tx_probe()
1213 return -ENODEV; in stm32_serial_probe()
1215 match = of_match_device(stm32_match, &pdev->dev); in stm32_serial_probe()
1216 if (match && match->data) in stm32_serial_probe()
1217 stm32port->info = (struct stm32_usart_info *)match->data; in stm32_serial_probe()
1219 return -EINVAL; in stm32_serial_probe()
1225 if (stm32port->wakeirq > 0) { in stm32_serial_probe()
1226 ret = device_init_wakeup(&pdev->dev, true); in stm32_serial_probe()
1230 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, in stm32_serial_probe()
1231 stm32port->wakeirq); in stm32_serial_probe()
1235 device_set_wakeup_enable(&pdev->dev, false); in stm32_serial_probe()
1238 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); in stm32_serial_probe()
1244 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n"); in stm32_serial_probe()
1248 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n"); in stm32_serial_probe()
1250 platform_set_drvdata(pdev, &stm32port->port); in stm32_serial_probe()
1252 pm_runtime_get_noresume(&pdev->dev); in stm32_serial_probe()
1253 pm_runtime_set_active(&pdev->dev); in stm32_serial_probe()
1254 pm_runtime_enable(&pdev->dev); in stm32_serial_probe()
1255 pm_runtime_put_sync(&pdev->dev); in stm32_serial_probe()
1260 if (stm32port->wakeirq > 0) in stm32_serial_probe()
1261 dev_pm_clear_wake_irq(&pdev->dev); in stm32_serial_probe()
1264 if (stm32port->wakeirq > 0) in stm32_serial_probe()
1265 device_init_wakeup(&pdev->dev, false); in stm32_serial_probe()
1268 clk_disable_unprepare(stm32port->clk); in stm32_serial_probe()
1277 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_serial_remove()
1280 pm_runtime_get_sync(&pdev->dev); in stm32_serial_remove()
1282 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_serial_remove()
1284 if (stm32_port->rx_ch) in stm32_serial_remove()
1285 dma_release_channel(stm32_port->rx_ch); in stm32_serial_remove()
1287 if (stm32_port->rx_dma_buf) in stm32_serial_remove()
1288 dma_free_coherent(&pdev->dev, in stm32_serial_remove()
1289 RX_BUF_L, stm32_port->rx_buf, in stm32_serial_remove()
1290 stm32_port->rx_dma_buf); in stm32_serial_remove()
1292 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_serial_remove()
1294 if (stm32_port->tx_ch) in stm32_serial_remove()
1295 dma_release_channel(stm32_port->tx_ch); in stm32_serial_remove()
1297 if (stm32_port->tx_dma_buf) in stm32_serial_remove()
1298 dma_free_coherent(&pdev->dev, in stm32_serial_remove()
1299 TX_BUF_L, stm32_port->tx_buf, in stm32_serial_remove()
1300 stm32_port->tx_dma_buf); in stm32_serial_remove()
1302 if (stm32_port->wakeirq > 0) { in stm32_serial_remove()
1303 dev_pm_clear_wake_irq(&pdev->dev); in stm32_serial_remove()
1304 device_init_wakeup(&pdev->dev, false); in stm32_serial_remove()
1307 clk_disable_unprepare(stm32_port->clk); in stm32_serial_remove()
1311 pm_runtime_disable(&pdev->dev); in stm32_serial_remove()
1312 pm_runtime_put_noidle(&pdev->dev); in stm32_serial_remove()
1322 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_console_putchar()
1324 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_console_putchar()
1327 writel_relaxed(ch, port->membase + ofs->tdr); in stm32_console_putchar()
1332 struct uart_port *port = &stm32_ports[co->index].port; in stm32_console_write()
1334 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_console_write()
1335 struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_console_write()
1341 if (port->sysrq) in stm32_console_write()
1344 locked = spin_trylock(&port->lock); in stm32_console_write()
1346 spin_lock(&port->lock); in stm32_console_write()
1349 old_cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_console_write()
1351 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); in stm32_console_write()
1352 writel_relaxed(new_cr1, port->membase + ofs->cr1); in stm32_console_write()
1357 writel_relaxed(old_cr1, port->membase + ofs->cr1); in stm32_console_write()
1360 spin_unlock(&port->lock); in stm32_console_write()
1372 if (co->index >= STM32_MAX_PORTS) in stm32_console_setup()
1373 return -ENODEV; in stm32_console_setup()
1375 stm32port = &stm32_ports[co->index]; in stm32_console_setup()
1383 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL) in stm32_console_setup()
1384 return -ENXIO; in stm32_console_setup()
1389 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); in stm32_console_setup()
1398 .index = -1,
1421 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_serial_enable_wakeup()
1422 struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_serial_enable_wakeup()
1425 if (stm32_port->wakeirq <= 0) in stm32_serial_enable_wakeup()
1429 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_serial_enable_wakeup()
1430 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_serial_enable_wakeup()
1431 val = readl_relaxed(port->membase + ofs->cr3); in stm32_serial_enable_wakeup()
1435 writel_relaxed(val, port->membase + ofs->cr3); in stm32_serial_enable_wakeup()
1436 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_serial_enable_wakeup()
1438 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_serial_enable_wakeup()
1487 clk_disable_unprepare(stm32port->clk); in stm32_serial_runtime_suspend()
1498 return clk_prepare_enable(stm32port->clk); in stm32_serial_runtime_resume()