495 #define sci_getreg(up, offset)		(&to_sci_port(up)->params->regs[offset])  macro
505 	const struct plat_sci_reg *reg = sci_getreg(p, offset);  in sci_serial_in()
519 	const struct plat_sci_reg *reg = sci_getreg(p, offset);  in sci_serial_out()
737 	} else if (sci_getreg(port, SCSPTR)->size) {  in sci_init_pins()
758 	reg = sci_getreg(port, SCTFDR);  in sci_txfill()
762 	reg = sci_getreg(port, SCFDR);  in sci_txfill()
780 	reg = sci_getreg(port, SCRFDR);  in sci_rxfill()
784 	reg = sci_getreg(port, SCFDR);  in sci_rxfill()
974 	reg = sci_getreg(port, s->params->overrun_reg);  in sci_handle_fifo_overrun()
1032 	if (sci_getreg(port, HSRTRGR)->size) {  in scif_set_rtrg()
1083 	if (sci_getreg(port, HSRTRGR)->size)  in scif_rtrg_enabled()
1545 			(sci_getreg(port, SCxTDR)->offset << port->regshift);  in sci_request_dma_chan()
1549 			(sci_getreg(port, SCxRDR)->offset << port->regshift);  in sci_request_dma_chan()
1811 	else if (sci_getreg(port, s->params->overrun_reg)->size)  in sci_mpxed_interrupt()
2009 	} else if (sci_getreg(port, SCSPTR)->size) {  in sci_set_rts()
2026 	} else if (sci_getreg(port, SCSPTR)->size) {  in sci_get_cts()
2056 		reg = sci_getreg(port, SCFCR);  in sci_set_mctrl()
2128 	if (!sci_getreg(port, SCSPTR)->size) {  in sci_break_ctl()
2342 	reg = sci_getreg(port, SCFCR);  in sci_reset()
2349 	if (sci_getreg(port, SCLSR)->size) {  in sci_reset()
2432 	if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {  in sci_set_termios()
2448 	if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {  in sci_set_termios()
2485 	if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {  in sci_set_termios()
2533 		if (sci_getreg(port, HSSRR)->size) {  in sci_set_termios()
2572 	reg = sci_getreg(port, SCFCR);  in sci_set_termios()