Lines Matching +full:cts +full:- +full:rts +full:- +full:swap
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
16 #include <linux/qcom-geni-se.h>
100 /* UART pin swap value */
199 struct platform_device *pdev = to_platform_device(uport->dev); in qcom_geni_serial_request_port()
202 uport->membase = devm_platform_ioremap_resource(pdev, 0); in qcom_geni_serial_request_port()
203 if (IS_ERR(uport->membase)) in qcom_geni_serial_request_port()
204 return PTR_ERR(uport->membase); in qcom_geni_serial_request_port()
205 port->se.base = uport->membase; in qcom_geni_serial_request_port()
212 uport->type = PORT_MSM; in qcom_geni_serial_config_port()
225 geni_ios = readl(uport->membase + SE_GENI_IOS); in qcom_geni_serial_get_mctrl()
243 port->loopback = RX_TX_CTS_RTS_SORTED; in qcom_geni_serial_set_mctrl()
245 if (!(mctrl & TIOCM_RTS) && !uport->suspended) in qcom_geni_serial_set_mctrl()
247 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_serial_set_mctrl()
261 return ERR_PTR(-ENXIO); in get_port_from_line()
275 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_poll_bit()
277 if (private_data->drv) { in qcom_geni_serial_poll_bit()
279 baud = port->baud; in qcom_geni_serial_poll_bit()
282 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; in qcom_geni_serial_poll_bit()
296 reg = readl(uport->membase + offset); in qcom_geni_serial_poll_bit()
300 timeout_us -= 10; in qcom_geni_serial_poll_bit()
309 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); in qcom_geni_serial_setup_tx()
311 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); in qcom_geni_serial_setup_tx()
322 writel(M_GENI_CMD_ABORT, uport->membase + in qcom_geni_serial_poll_tx_done()
328 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_poll_tx_done()
335 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); in qcom_geni_serial_abort_rx()
338 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_abort_rx()
339 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); in qcom_geni_serial_abort_rx()
346 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_get_char()
351 if (!private_data->poll_cached_bytes_cnt) { in qcom_geni_serial_get_char()
352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); in qcom_geni_serial_get_char()
353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_get_char()
355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); in qcom_geni_serial_get_char()
356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_get_char()
358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); in qcom_geni_serial_get_char()
368 private_data->poll_cached_bytes_cnt = in qcom_geni_serial_get_char()
372 if (private_data->poll_cached_bytes_cnt == 0) in qcom_geni_serial_get_char()
373 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; in qcom_geni_serial_get_char()
375 private_data->poll_cached_bytes = in qcom_geni_serial_get_char()
376 readl(uport->membase + SE_GENI_RX_FIFOn); in qcom_geni_serial_get_char()
379 private_data->poll_cached_bytes_cnt--; in qcom_geni_serial_get_char()
380 ret = private_data->poll_cached_bytes & 0xff; in qcom_geni_serial_get_char()
381 private_data->poll_cached_bytes >>= 8; in qcom_geni_serial_get_char()
389 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); in qcom_geni_serial_poll_put_char()
393 writel(c, uport->membase + SE_GENI_TX_FIFOn); in qcom_geni_serial_poll_put_char()
394 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_poll_put_char()
402 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_wr_char()
404 private_data->write_cached_bytes = in qcom_geni_serial_wr_char()
405 (private_data->write_cached_bytes >> 8) | (ch << 24); in qcom_geni_serial_wr_char()
406 private_data->write_cached_bytes_cnt++; in qcom_geni_serial_wr_char()
408 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { in qcom_geni_serial_wr_char()
409 writel(private_data->write_cached_bytes, in qcom_geni_serial_wr_char()
410 uport->membase + SE_GENI_TX_FIFOn); in qcom_geni_serial_wr_char()
411 private_data->write_cached_bytes_cnt = 0; in qcom_geni_serial_wr_char()
419 struct qcom_geni_private_data *private_data = uport->private_data; in __qcom_geni_serial_console_write()
433 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); in __qcom_geni_serial_console_write()
437 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; in __qcom_geni_serial_console_write()
448 chars_to_write = min_t(size_t, count - i, avail / 2); in __qcom_geni_serial_console_write()
451 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + in __qcom_geni_serial_console_write()
456 if (private_data->write_cached_bytes_cnt) { in __qcom_geni_serial_console_write()
457 private_data->write_cached_bytes >>= BITS_PER_BYTE * in __qcom_geni_serial_console_write()
458 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); in __qcom_geni_serial_console_write()
459 writel(private_data->write_cached_bytes, in __qcom_geni_serial_console_write()
460 uport->membase + SE_GENI_TX_FIFOn); in __qcom_geni_serial_console_write()
461 private_data->write_cached_bytes_cnt = 0; in __qcom_geni_serial_console_write()
477 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); in qcom_geni_serial_console_write()
479 port = get_port_from_line(co->index, true); in qcom_geni_serial_console_write()
483 uport = &port->uport; in qcom_geni_serial_console_write()
485 locked = spin_trylock_irqsave(&uport->lock, flags); in qcom_geni_serial_console_write()
487 spin_lock_irqsave(&uport->lock, flags); in qcom_geni_serial_console_write()
489 geni_status = readl(uport->membase + SE_GENI_STATUS); in qcom_geni_serial_console_write()
493 geni_se_cancel_m_cmd(&port->se); in qcom_geni_serial_console_write()
496 geni_se_abort_m_cmd(&port->se); in qcom_geni_serial_console_write()
499 writel(M_CMD_ABORT_EN, uport->membase + in qcom_geni_serial_console_write()
502 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_console_write()
503 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { in qcom_geni_serial_console_write()
510 if (uart_circ_chars_pending(&uport->state->xmit)) { in qcom_geni_serial_console_write()
511 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_console_write()
513 uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_console_write()
519 if (port->tx_remaining) in qcom_geni_serial_console_write()
520 qcom_geni_serial_setup_tx(uport, port->tx_remaining); in qcom_geni_serial_console_write()
523 spin_unlock_irqrestore(&uport->lock, flags); in qcom_geni_serial_console_write()
533 tport = &uport->state->port; in handle_rx_console()
536 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); in handle_rx_console()
538 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); in handle_rx_console()
546 uport->icount.rx++; in handle_rx_console()
547 if (port->brk && buf[c] == 0) { in handle_rx_console()
548 port->brk = false; in handle_rx_console()
566 return -EPERM; in handle_rx_console()
575 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE; in handle_rx_uart()
579 tport = &uport->state->port; in handle_rx_uart()
580 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words); in handle_rx_uart()
584 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes); in handle_rx_uart()
586 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", in handle_rx_uart()
590 uport->icount.rx += ret; in handle_rx_uart()
600 status = readl(uport->membase + SE_GENI_STATUS); in qcom_geni_serial_start_tx()
607 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_tx()
610 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); in qcom_geni_serial_start_tx()
611 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_tx()
620 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_tx()
622 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); in qcom_geni_serial_stop_tx()
623 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_tx()
624 status = readl(uport->membase + SE_GENI_STATUS); in qcom_geni_serial_stop_tx()
629 geni_se_cancel_m_cmd(&port->se); in qcom_geni_serial_stop_tx()
632 geni_se_abort_m_cmd(&port->se); in qcom_geni_serial_stop_tx()
635 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_stop_tx()
637 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_stop_tx()
646 status = readl(uport->membase + SE_GENI_STATUS); in qcom_geni_serial_start_rx()
650 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); in qcom_geni_serial_start_rx()
652 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_start_rx()
654 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_start_rx()
656 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_rx()
658 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_start_rx()
668 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_stop_rx()
670 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); in qcom_geni_serial_stop_rx()
672 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_rx()
674 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_stop_rx()
676 status = readl(uport->membase + SE_GENI_STATUS); in qcom_geni_serial_stop_rx()
681 geni_se_cancel_s_cmd(&port->se); in qcom_geni_serial_stop_rx()
688 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); in qcom_geni_serial_stop_rx()
692 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_stop_rx()
694 status = readl(uport->membase + SE_GENI_STATUS); in qcom_geni_serial_stop_rx()
708 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); in qcom_geni_serial_handle_rx()
716 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); in qcom_geni_serial_handle_rx()
721 port->handle_rx(uport, total_bytes, drop); in qcom_geni_serial_handle_rx()
728 struct circ_buf *xmit = &uport->state->xmit; in qcom_geni_serial_handle_tx()
738 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); in qcom_geni_serial_handle_tx()
742 pending = port->tx_remaining; in qcom_geni_serial_handle_tx()
752 avail = port->tx_fifo_depth - (status & TX_FIFO_WC); in qcom_geni_serial_handle_tx()
755 tail = xmit->tail; in qcom_geni_serial_handle_tx()
760 if (!port->tx_remaining) { in qcom_geni_serial_handle_tx()
762 port->tx_remaining = pending; in qcom_geni_serial_handle_tx()
764 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx()
767 uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx()
780 buf[c] = xmit->buf[tail++]; in qcom_geni_serial_handle_tx()
781 tail &= UART_XMIT_SIZE - 1; in qcom_geni_serial_handle_tx()
784 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); in qcom_geni_serial_handle_tx()
787 uport->icount.tx += tx_bytes; in qcom_geni_serial_handle_tx()
788 remaining -= tx_bytes; in qcom_geni_serial_handle_tx()
789 port->tx_remaining -= tx_bytes; in qcom_geni_serial_handle_tx()
792 xmit->tail = tail; in qcom_geni_serial_handle_tx()
800 uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_handle_tx()
803 if (!port->tx_remaining) { in qcom_geni_serial_handle_tx()
804 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx()
807 uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_handle_tx()
823 struct tty_port *tport = &uport->state->port; in qcom_geni_serial_isr()
826 if (uport->suspended) in qcom_geni_serial_isr()
829 spin_lock_irqsave(&uport->lock, flags); in qcom_geni_serial_isr()
830 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); in qcom_geni_serial_isr()
831 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); in qcom_geni_serial_isr()
832 geni_status = readl(uport->membase + SE_GENI_STATUS); in qcom_geni_serial_isr()
833 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); in qcom_geni_serial_isr()
834 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_isr()
835 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); in qcom_geni_serial_isr()
841 uport->icount.overrun++; in qcom_geni_serial_isr()
851 uport->icount.parity++; in qcom_geni_serial_isr()
855 uport->icount.brk++; in qcom_geni_serial_isr()
856 port->brk = true; in qcom_geni_serial_isr()
873 uport = &port->uport; in get_tx_fifo_size()
874 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); in get_tx_fifo_size()
875 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); in get_tx_fifo_size()
876 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); in get_tx_fifo_size()
877 uport->fifosize = in get_tx_fifo_size()
878 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; in get_tx_fifo_size()
884 disable_irq(uport->irq); in qcom_geni_serial_shutdown()
894 proto = geni_se_read_proto(&port->se); in qcom_geni_serial_port_setup()
896 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); in qcom_geni_serial_port_setup()
897 return -ENXIO; in qcom_geni_serial_port_setup()
904 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); in qcom_geni_serial_port_setup()
906 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); in qcom_geni_serial_port_setup()
907 if (port->rx_tx_swap) { in qcom_geni_serial_port_setup()
911 if (port->cts_rts_swap) { in qcom_geni_serial_port_setup()
915 /* Configure this register if RX-TX, CTS-RTS pins are swapped */ in qcom_geni_serial_port_setup()
916 if (port->rx_tx_swap || port->cts_rts_swap) in qcom_geni_serial_port_setup()
917 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); in qcom_geni_serial_port_setup()
925 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, in qcom_geni_serial_port_setup()
927 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); in qcom_geni_serial_port_setup()
928 geni_se_select_mode(&port->se, GENI_SE_FIFO); in qcom_geni_serial_port_setup()
929 port->setup = true; in qcom_geni_serial_port_setup()
939 if (!port->setup) { in qcom_geni_serial_startup()
944 enable_irq(uport->irq); in qcom_geni_serial_startup()
998 port->baud = baud; in qcom_geni_serial_set_termios()
1002 ver = geni_se_get_qup_hw_version(&port->se); in qcom_geni_serial_set_termios()
1010 uport->uartclk = clk_rate; in qcom_geni_serial_set_termios()
1011 dev_pm_opp_set_rate(uport->dev, clk_rate); in qcom_geni_serial_set_termios()
1021 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; in qcom_geni_serial_set_termios()
1022 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); in qcom_geni_serial_set_termios()
1023 geni_icc_set_bw(&port->se); in qcom_geni_serial_set_termios()
1026 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); in qcom_geni_serial_set_termios()
1027 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); in qcom_geni_serial_set_termios()
1028 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); in qcom_geni_serial_set_termios()
1029 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); in qcom_geni_serial_set_termios()
1030 if (termios->c_cflag & PARENB) { in qcom_geni_serial_set_termios()
1035 if (termios->c_cflag & PARODD) { in qcom_geni_serial_set_termios()
1038 } else if (termios->c_cflag & CMSPAR) { in qcom_geni_serial_set_termios()
1053 switch (termios->c_cflag & CSIZE) { in qcom_geni_serial_set_termios()
1070 if (termios->c_cflag & CSTOPB) in qcom_geni_serial_set_termios()
1076 if (termios->c_cflag & CRTSCTS) in qcom_geni_serial_set_termios()
1082 uart_update_timeout(uport, termios->c_cflag, baud); in qcom_geni_serial_set_termios()
1085 writel(port->loopback, in qcom_geni_serial_set_termios()
1086 uport->membase + SE_UART_LOOPBACK_CFG); in qcom_geni_serial_set_termios()
1087 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); in qcom_geni_serial_set_termios()
1088 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); in qcom_geni_serial_set_termios()
1089 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); in qcom_geni_serial_set_termios()
1090 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); in qcom_geni_serial_set_termios()
1091 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); in qcom_geni_serial_set_termios()
1092 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); in qcom_geni_serial_set_termios()
1093 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); in qcom_geni_serial_set_termios()
1094 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); in qcom_geni_serial_set_termios()
1095 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); in qcom_geni_serial_set_termios()
1102 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); in qcom_geni_serial_tx_empty()
1116 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) in qcom_geni_console_setup()
1117 return -ENXIO; in qcom_geni_console_setup()
1119 port = get_port_from_line(co->index, true); in qcom_geni_console_setup()
1121 pr_err("Invalid line %d\n", co->index); in qcom_geni_console_setup()
1125 uport = &port->uport; in qcom_geni_console_setup()
1127 if (unlikely(!uport->membase)) in qcom_geni_console_setup()
1128 return -ENXIO; in qcom_geni_console_setup()
1130 if (!port->setup) { in qcom_geni_console_setup()
1145 struct earlycon_device *dev = con->data; in qcom_geni_serial_earlycon_write()
1147 __qcom_geni_serial_console_write(&dev->port, s, n); in qcom_geni_serial_earlycon_write()
1154 struct earlycon_device *dev = con->data; in qcom_geni_serial_earlycon_read()
1155 struct uart_port *uport = &dev->port; in qcom_geni_serial_earlycon_read()
1173 con->read = qcom_geni_serial_earlycon_read; in qcom_geni_serial_enable_early_read()
1191 struct uart_port *uport = &dev->port; in qcom_geni_serial_earlycon_setup()
1196 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ in qcom_geni_serial_earlycon_setup()
1200 if (!uport->membase) in qcom_geni_serial_earlycon_setup()
1201 return -EINVAL; in qcom_geni_serial_earlycon_setup()
1203 uport->private_data = &earlycon_private_data; in qcom_geni_serial_earlycon_setup()
1206 se.base = uport->membase; in qcom_geni_serial_earlycon_setup()
1208 return -ENXIO; in qcom_geni_serial_earlycon_setup()
1224 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); in qcom_geni_serial_earlycon_setup()
1227 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); in qcom_geni_serial_earlycon_setup()
1228 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); in qcom_geni_serial_earlycon_setup()
1229 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); in qcom_geni_serial_earlycon_setup()
1230 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); in qcom_geni_serial_earlycon_setup()
1231 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); in qcom_geni_serial_earlycon_setup()
1232 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); in qcom_geni_serial_earlycon_setup()
1233 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); in qcom_geni_serial_earlycon_setup()
1235 dev->con->write = qcom_geni_serial_earlycon_write; in qcom_geni_serial_earlycon_setup()
1236 dev->con->exit = qcom_geni_serial_earlycon_exit; in qcom_geni_serial_earlycon_setup()
1237 dev->con->setup = NULL; in qcom_geni_serial_earlycon_setup()
1238 qcom_geni_serial_enable_early_read(&se, dev->con); in qcom_geni_serial_earlycon_setup()
1242 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1261 .index = -1,
1300 geni_icc_enable(&port->se); in qcom_geni_serial_pm()
1301 geni_se_resources_on(&port->se); in qcom_geni_serial_pm()
1304 geni_se_resources_off(&port->se); in qcom_geni_serial_pm()
1305 geni_icc_disable(&port->se); in qcom_geni_serial_pm()
1348 int line = -1; in qcom_geni_serial_probe()
1356 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart")) in qcom_geni_serial_probe()
1361 line = of_alias_get_id(pdev->dev.of_node, "serial"); in qcom_geni_serial_probe()
1364 line = of_alias_get_id(pdev->dev.of_node, "hsuart"); in qcom_geni_serial_probe()
1369 dev_err(&pdev->dev, "Invalid line %d\n", line); in qcom_geni_serial_probe()
1373 uport = &port->uport; in qcom_geni_serial_probe()
1375 if (uport->private_data) in qcom_geni_serial_probe()
1376 return -ENODEV; in qcom_geni_serial_probe()
1378 uport->dev = &pdev->dev; in qcom_geni_serial_probe()
1379 port->se.dev = &pdev->dev; in qcom_geni_serial_probe()
1380 port->se.wrapper = dev_get_drvdata(pdev->dev.parent); in qcom_geni_serial_probe()
1381 port->se.clk = devm_clk_get(&pdev->dev, "se"); in qcom_geni_serial_probe()
1382 if (IS_ERR(port->se.clk)) { in qcom_geni_serial_probe()
1383 ret = PTR_ERR(port->se.clk); in qcom_geni_serial_probe()
1384 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); in qcom_geni_serial_probe()
1390 return -EINVAL; in qcom_geni_serial_probe()
1391 uport->mapbase = res->start; in qcom_geni_serial_probe()
1393 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; in qcom_geni_serial_probe()
1394 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; in qcom_geni_serial_probe()
1395 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; in qcom_geni_serial_probe()
1398 port->rx_fifo = devm_kcalloc(uport->dev, in qcom_geni_serial_probe()
1399 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL); in qcom_geni_serial_probe()
1400 if (!port->rx_fifo) in qcom_geni_serial_probe()
1401 return -ENOMEM; in qcom_geni_serial_probe()
1404 ret = geni_icc_get(&port->se, NULL); in qcom_geni_serial_probe()
1407 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; in qcom_geni_serial_probe()
1408 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in qcom_geni_serial_probe()
1411 ret = geni_icc_set_bw(&port->se); in qcom_geni_serial_probe()
1415 port->name = devm_kasprintf(uport->dev, GFP_KERNEL, in qcom_geni_serial_probe()
1417 uart_console(uport) ? "console" : "uart", uport->line); in qcom_geni_serial_probe()
1418 if (!port->name) in qcom_geni_serial_probe()
1419 return -ENOMEM; in qcom_geni_serial_probe()
1424 uport->irq = irq; in qcom_geni_serial_probe()
1425 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); in qcom_geni_serial_probe()
1428 port->wakeup_irq = platform_get_irq_optional(pdev, 1); in qcom_geni_serial_probe()
1430 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) in qcom_geni_serial_probe()
1431 port->rx_tx_swap = true; in qcom_geni_serial_probe()
1433 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) in qcom_geni_serial_probe()
1434 port->cts_rts_swap = true; in qcom_geni_serial_probe()
1436 port->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se"); in qcom_geni_serial_probe()
1437 if (IS_ERR(port->se.opp_table)) in qcom_geni_serial_probe()
1438 return PTR_ERR(port->se.opp_table); in qcom_geni_serial_probe()
1440 ret = dev_pm_opp_of_add_table(&pdev->dev); in qcom_geni_serial_probe()
1441 if (ret && ret != -ENODEV) { in qcom_geni_serial_probe()
1442 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); in qcom_geni_serial_probe()
1446 port->private_data.drv = drv; in qcom_geni_serial_probe()
1447 uport->private_data = &port->private_data; in qcom_geni_serial_probe()
1449 port->handle_rx = console ? handle_rx_console : handle_rx_uart; in qcom_geni_serial_probe()
1455 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); in qcom_geni_serial_probe()
1456 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, in qcom_geni_serial_probe()
1457 IRQF_TRIGGER_HIGH, port->name, uport); in qcom_geni_serial_probe()
1459 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); in qcom_geni_serial_probe()
1469 pm_runtime_set_active(&pdev->dev); in qcom_geni_serial_probe()
1471 if (port->wakeup_irq > 0) { in qcom_geni_serial_probe()
1472 device_init_wakeup(&pdev->dev, true); in qcom_geni_serial_probe()
1473 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, in qcom_geni_serial_probe()
1474 port->wakeup_irq); in qcom_geni_serial_probe()
1476 device_init_wakeup(&pdev->dev, false); in qcom_geni_serial_probe()
1484 dev_pm_opp_of_remove_table(&pdev->dev); in qcom_geni_serial_probe()
1486 dev_pm_opp_put_clkname(port->se.opp_table); in qcom_geni_serial_probe()
1493 struct uart_driver *drv = port->private_data.drv; in qcom_geni_serial_remove()
1495 dev_pm_opp_of_remove_table(&pdev->dev); in qcom_geni_serial_remove()
1496 dev_pm_opp_put_clkname(port->se.opp_table); in qcom_geni_serial_remove()
1497 dev_pm_clear_wake_irq(&pdev->dev); in qcom_geni_serial_remove()
1498 device_init_wakeup(&pdev->dev, false); in qcom_geni_serial_remove()
1499 uart_remove_one_port(drv, &port->uport); in qcom_geni_serial_remove()
1507 struct uart_port *uport = &port->uport; in qcom_geni_serial_sys_suspend()
1508 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_sys_suspend()
1515 geni_icc_set_tag(&port->se, 0x3); in qcom_geni_serial_sys_suspend()
1516 geni_icc_set_bw(&port->se); in qcom_geni_serial_sys_suspend()
1518 return uart_suspend_port(private_data->drv, uport); in qcom_geni_serial_sys_suspend()
1525 struct uart_port *uport = &port->uport; in qcom_geni_serial_sys_resume()
1526 struct qcom_geni_private_data *private_data = uport->private_data; in qcom_geni_serial_sys_resume()
1528 ret = uart_resume_port(private_data->drv, uport); in qcom_geni_serial_sys_resume()
1530 geni_icc_set_tag(&port->se, 0x7); in qcom_geni_serial_sys_resume()
1531 geni_icc_set_bw(&port->se); in qcom_geni_serial_sys_resume()
1542 { .compatible = "qcom,geni-debug-uart", },
1543 { .compatible = "qcom,geni-uart", },