164 	st = readl(port->membase + UART_STAT);  in mvebu_uart_tx_empty()
186 	unsigned int ctl = readl(port->membase + UART_INTR(port));  in mvebu_uart_stop_tx()
189 	writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_stop_tx()
198 		writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));  in mvebu_uart_start_tx()
203 	ctl = readl(port->membase + UART_INTR(port));  in mvebu_uart_start_tx()
205 	writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_start_tx()
212 	ctl = readl(port->membase + UART_CTRL(port));  in mvebu_uart_stop_rx()
214 	writel(ctl, port->membase + UART_CTRL(port));  in mvebu_uart_stop_rx()
216 	ctl = readl(port->membase + UART_INTR(port));  in mvebu_uart_stop_rx()
218 	writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_stop_rx()
227 	ctl = readl(port->membase + UART_CTRL(port));  in mvebu_uart_break_ctl()
232 	writel(ctl, port->membase + UART_CTRL(port));  in mvebu_uart_break_ctl()
244 			ch = readl(port->membase + UART_RBR(port));  in mvebu_uart_rx_chars()
292 		status = readl(port->membase + UART_STAT);  in mvebu_uart_rx_chars()
305 		writel(port->x_char, port->membase + UART_TSH(port));  in mvebu_uart_tx_chars()
317 		writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));  in mvebu_uart_tx_chars()
324 		st = readl(port->membase + UART_STAT);  in mvebu_uart_tx_chars()
339 	unsigned int st = readl(port->membase + UART_STAT);  in mvebu_uart_isr()
354 	unsigned int st = readl(port->membase + UART_STAT);  in mvebu_uart_rx_isr()
366 	unsigned int st = readl(port->membase + UART_STAT);  in mvebu_uart_tx_isr()
381 	       port->membase + UART_CTRL(port));  in mvebu_uart_startup()
385 	ret = readl(port->membase + UART_STAT);  in mvebu_uart_startup()
387 	writel(ret, port->membase + UART_STAT);  in mvebu_uart_startup()
389 	writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));  in mvebu_uart_startup()
391 	ctl = readl(port->membase + UART_INTR(port));  in mvebu_uart_startup()
393 	writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_startup()
436 	writel(0, port->membase + UART_INTR(port));  in mvebu_uart_shutdown()
468 	brdv = readl(port->membase + UART_BRDV);  in mvebu_uart_baud_rate_set()
471 	writel(brdv, port->membase + UART_BRDV);  in mvebu_uart_baud_rate_set()
473 	osamp = readl(port->membase + UART_OSAMP);  in mvebu_uart_baud_rate_set()
475 	writel(osamp, port->membase + UART_OSAMP);  in mvebu_uart_baud_rate_set()
549 	unsigned int st = readl(port->membase + UART_STAT);  in mvebu_uart_get_poll_char()
554 	return readl(port->membase + UART_RBR(port));  in mvebu_uart_get_poll_char()
562 		st = readl(port->membase + UART_STAT);  in mvebu_uart_put_poll_char()
570 	writel(c, port->membase + UART_TSH(port));  in mvebu_uart_put_poll_char()
603 		st = readl(port->membase + UART_STAT);  in mvebu_uart_putc()
609 	writel(c, port->membase + UART_STD_TSH);  in mvebu_uart_putc()
612 		st = readl(port->membase + UART_STAT);  in mvebu_uart_putc()
631 	if (!device->port.membase)  in mvebu_uart_early_console_setup()
647 	readl_poll_timeout_atomic(port->membase + UART_STAT, val,  in wait_for_xmitr()
654 	writel(ch, port->membase + UART_TSH(port));  in mvebu_uart_console_putchar()
670 	ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;  in mvebu_uart_console_write()
671 	intr = readl(port->membase + UART_INTR(port)) &  in mvebu_uart_console_write()
673 	writel(0, port->membase + UART_CTRL(port));  in mvebu_uart_console_write()
674 	writel(0, port->membase + UART_INTR(port));  in mvebu_uart_console_write()
681 		writel(ier, port->membase + UART_CTRL(port));  in mvebu_uart_console_write()
684 		ctl = intr | readl(port->membase + UART_INTR(port));  in mvebu_uart_console_write()
685 		writel(ctl, port->membase + UART_INTR(port));  in mvebu_uart_console_write()
705 	if (!port->mapbase || !port->membase) {  in mvebu_uart_console_setup()
757 	mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));  in mvebu_uart_suspend()
758 	mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));  in mvebu_uart_suspend()
759 	mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));  in mvebu_uart_suspend()
760 	mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));  in mvebu_uart_suspend()
761 	mvuart->pm_regs.stat = readl(port->membase + UART_STAT);  in mvebu_uart_suspend()
762 	mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);  in mvebu_uart_suspend()
763 	mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);  in mvebu_uart_suspend()
775 	writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));  in mvebu_uart_resume()
776 	writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));  in mvebu_uart_resume()
777 	writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));  in mvebu_uart_resume()
778 	writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));  in mvebu_uart_resume()
779 	writel(mvuart->pm_regs.stat, port->membase + UART_STAT);  in mvebu_uart_resume()
780 	writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);  in mvebu_uart_resume()
781 	writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);  in mvebu_uart_resume()
852 	port->membase = devm_ioremap_resource(&pdev->dev, reg);  in mvebu_uart_probe()
853 	if (IS_ERR(port->membase))  in mvebu_uart_probe()
854 		return PTR_ERR(port->membase);  in mvebu_uart_probe()
911 	writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));  in mvebu_uart_probe()
913 	writel(0, port->membase + UART_CTRL(port));  in mvebu_uart_probe()