Lines Matching +full:auto +full:- +full:baud
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
49 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
63 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
64 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
65 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
102 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
115 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
116 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
119 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
129 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
137 * 00 -> 5 bit words
138 * 01 -> 6 bit words
139 * 10 -> 7 bit words
140 * 11 -> 8 bit words
145 * 0 -> 1 stop bit
146 * 1 -> 1-1.5 stop bits if
152 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
173 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
174 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
179 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
184 * 00 -> no transmitter flow
186 * 01 -> receiver compares
190 * 10 -> receiver compares
194 * 11 -> receiver compares
203 * 00 -> no received flow
205 * 01 -> transmitter generates
207 * 10 -> transmitter generates
209 * 11 -> transmitter generates
218 /* Baud rate generator configuration register bits */
219 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
220 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
227 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
292 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_port_read()
295 regmap_read(s->regmap, port->iobase + reg, &val); in max310x_port_read()
302 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_port_write()
304 regmap_write(s->regmap, port->iobase + reg, val); in max310x_port_write()
309 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_port_update()
311 regmap_update_bits(s->regmap, port->iobase + reg, mask, val); in max310x_port_update()
320 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); in max3107_detect()
326 "%s ID 0x%02x does not match\n", s->devtype->name, val); in max3107_detect()
327 return -ENODEV; in max3107_detect()
342 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); in max3108_detect()
347 dev_err(dev, "%s not present\n", s->devtype->name); in max3108_detect()
348 return -ENODEV; in max3108_detect()
360 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, in max3109_detect()
365 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); in max3109_detect()
366 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); in max3109_detect()
369 "%s ID 0x%02x does not match\n", s->devtype->name, val); in max3109_detect()
370 return -ENODEV; in max3109_detect()
391 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, in max14830_detect()
396 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); in max14830_detect()
397 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); in max14830_detect()
400 "%s ID 0x%02x does not match\n", s->devtype->name, val); in max14830_detect()
401 return -ENODEV; in max14830_detect()
502 static int max310x_set_baud(struct uart_port *port, int baud) in max310x_set_baud() argument
508 * in case if the requested baud is too high for the pre-defined in max310x_set_baud()
511 div = port->uartclk / baud; in max310x_set_baud()
526 F = c*baud; in max310x_set_baud()
528 /* Calculate the baud rate fraction */ in max310x_set_baud()
530 frac = (16*(port->uartclk % F)) / F; in max310x_set_baud()
538 /* Return the actual baud rate we just programmed */ in max310x_set_baud()
539 return (16*port->uartclk) / (c*(16*div + frac)); in max310x_set_baud()
559 long besterr = -1; in max310x_set_ref_clk()
605 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); in max310x_set_ref_clk()
609 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); in max310x_set_ref_clk()
615 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); in max310x_set_ref_clk()
629 .tx_buf = &one->wr_header, in max310x_batch_write()
630 .len = sizeof(one->wr_header), in max310x_batch_write()
636 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer)); in max310x_batch_write()
644 .tx_buf = &one->rd_header, in max310x_batch_read()
645 .len = sizeof(one->rd_header), in max310x_batch_read()
651 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer)); in max310x_batch_read()
659 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { in max310x_handle_rx()
661 * Break condition, parity checking, framing errors -- they in max310x_handle_rx()
662 * are all ignored. That means that we can do a batch-read. in max310x_handle_rx()
672 max310x_batch_read(port, one->rx_buf, rxlen); in max310x_handle_rx()
674 port->icount.rx += rxlen; in max310x_handle_rx()
676 sts &= port->read_status_mask; in max310x_handle_rx()
679 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); in max310x_handle_rx()
680 port->icount.overrun++; in max310x_handle_rx()
683 for (i = 0; i < (rxlen - 1); ++i) in max310x_handle_rx()
684 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); in max310x_handle_rx()
692 one->rx_buf[rxlen-1], flag); in max310x_handle_rx()
695 if (unlikely(rxlen >= port->fifosize)) { in max310x_handle_rx()
696 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); in max310x_handle_rx()
697 port->icount.buf_overrun++; in max310x_handle_rx()
699 rxlen = port->fifosize; in max310x_handle_rx()
702 while (rxlen--) { in max310x_handle_rx()
709 port->icount.rx++; in max310x_handle_rx()
714 port->icount.brk++; in max310x_handle_rx()
718 port->icount.parity++; in max310x_handle_rx()
720 port->icount.frame++; in max310x_handle_rx()
722 port->icount.overrun++; in max310x_handle_rx()
724 sts &= port->read_status_mask; in max310x_handle_rx()
738 if (sts & port->ignore_status_mask) in max310x_handle_rx()
745 tty_flip_buffer_push(&port->state->port); in max310x_handle_rx()
750 struct circ_buf *xmit = &port->state->xmit; in max310x_handle_tx()
753 if (unlikely(port->x_char)) { in max310x_handle_tx()
754 max310x_port_write(port, MAX310X_THR_REG, port->x_char); in max310x_handle_tx()
755 port->icount.tx++; in max310x_handle_tx()
756 port->x_char = 0; in max310x_handle_tx()
765 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); in max310x_handle_tx()
769 txlen = port->fifosize - txlen; in max310x_handle_tx()
773 /* It's a circ buffer -- wrap around. in max310x_handle_tx()
775 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); in max310x_handle_tx()
776 max310x_batch_write(port, xmit->buf, to_send - until_end); in max310x_handle_tx()
778 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); in max310x_handle_tx()
782 port->icount.tx += to_send; in max310x_handle_tx()
783 xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1); in max310x_handle_tx()
794 schedule_work(&one->tx_work); in max310x_start_tx()
799 struct uart_port *port = &s->p[portno].port; in max310x_port_irq()
831 if (s->devtype->nr > 1) { in max310x_ist()
835 WARN_ON_ONCE(regmap_read(s->regmap, in max310x_ist()
837 val = ((1 << s->devtype->nr) - 1) & ~val; in max310x_ist()
840 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) in max310x_ist()
855 max310x_handle_tx(&one->port); in max310x_tx_proc()
877 max310x_port_update(&one->port, MAX310X_MODE2_REG, in max310x_md_proc()
879 (one->port.mctrl & TIOCM_LOOP) ? in max310x_md_proc()
887 schedule_work(&one->md_work); in max310x_set_mctrl()
902 int baud; in max310x_set_termios() local
905 termios->c_cflag &= ~CMSPAR; in max310x_set_termios()
908 switch (termios->c_cflag & CSIZE) { in max310x_set_termios()
924 if (termios->c_cflag & PARENB) { in max310x_set_termios()
926 if (!(termios->c_cflag & PARODD)) in max310x_set_termios()
931 if (termios->c_cflag & CSTOPB) in max310x_set_termios()
938 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; in max310x_set_termios()
939 if (termios->c_iflag & INPCK) in max310x_set_termios()
940 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | in max310x_set_termios()
942 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in max310x_set_termios()
943 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; in max310x_set_termios()
946 port->ignore_status_mask = 0; in max310x_set_termios()
947 if (termios->c_iflag & IGNBRK) in max310x_set_termios()
948 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; in max310x_set_termios()
949 if (!(termios->c_cflag & CREAD)) in max310x_set_termios()
950 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | in max310x_set_termios()
956 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); in max310x_set_termios()
957 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); in max310x_set_termios()
959 /* Disable transmitter before enabling AutoCTS or auto transmitter in max310x_set_termios()
962 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { in max310x_set_termios()
968 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); in max310x_set_termios()
970 if (termios->c_cflag & CRTSCTS) { in max310x_set_termios()
972 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in max310x_set_termios()
976 if (termios->c_iflag & IXON) in max310x_set_termios()
979 if (termios->c_iflag & IXOFF) { in max310x_set_termios()
980 port->status |= UPSTAT_AUTOXOFF; in max310x_set_termios()
986 /* Enable transmitter after disabling AutoCTS and auto transmitter in max310x_set_termios()
989 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { in max310x_set_termios()
995 /* Get baud rate generator configuration */ in max310x_set_termios()
996 baud = uart_get_baud_rate(port, termios, old, in max310x_set_termios()
997 port->uartclk / 16 / 0xffff, in max310x_set_termios()
998 port->uartclk / 4); in max310x_set_termios()
1001 baud = max310x_set_baud(port, baud); in max310x_set_termios()
1003 /* Update timeout according to new baud rate */ in max310x_set_termios()
1004 uart_update_timeout(port, termios->c_cflag, baud); in max310x_set_termios()
1012 delay = (one->port.rs485.delay_rts_before_send << 4) | in max310x_rs_proc()
1013 one->port.rs485.delay_rts_after_send; in max310x_rs_proc()
1014 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); in max310x_rs_proc()
1016 if (one->port.rs485.flags & SER_RS485_ENABLED) { in max310x_rs_proc()
1019 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) in max310x_rs_proc()
1023 max310x_port_update(&one->port, MAX310X_MODE1_REG, in max310x_rs_proc()
1025 max310x_port_update(&one->port, MAX310X_MODE2_REG, in max310x_rs_proc()
1034 if ((rs485->delay_rts_before_send > 0x0f) || in max310x_rs485_config()
1035 (rs485->delay_rts_after_send > 0x0f)) in max310x_rs485_config()
1036 return -ERANGE; in max310x_rs485_config()
1038 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX | in max310x_rs485_config()
1040 memset(rs485->padding, 0, sizeof(rs485->padding)); in max310x_rs485_config()
1041 port->rs485 = *rs485; in max310x_rs485_config()
1043 schedule_work(&one->rs_work); in max310x_rs485_config()
1050 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_startup()
1053 s->devtype->power(port, 1); in max310x_startup()
1066 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | in max310x_startup()
1067 clamp(port->rs485.delay_rts_after_send, 0U, 15U); in max310x_startup()
1070 if (port->rs485.flags & SER_RS485_ENABLED) { in max310x_startup()
1075 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in max310x_startup()
1117 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_shutdown()
1122 s->devtype->power(port, 0); in max310x_shutdown()
1127 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_type()
1129 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; in max310x_type()
1141 port->type = PORT_MAX310X; in max310x_config_port()
1146 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) in max310x_verify_port()
1147 return -EINVAL; in max310x_verify_port()
1148 if (s->irq != port->irq) in max310x_verify_port()
1149 return -EINVAL; in max310x_verify_port()
1182 for (i = 0; i < s->devtype->nr; i++) { in max310x_suspend()
1183 uart_suspend_port(&max310x_uart, &s->p[i].port); in max310x_suspend()
1184 s->devtype->power(&s->p[i].port, 0); in max310x_suspend()
1195 for (i = 0; i < s->devtype->nr; i++) { in max310x_resume()
1196 s->devtype->power(&s->p[i].port, 1); in max310x_resume()
1197 uart_resume_port(&max310x_uart, &s->p[i].port); in max310x_resume()
1210 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_get()
1220 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_set()
1229 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_direction_input()
1240 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_direction_output()
1254 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_set_config()
1267 return -ENOTSUPP; in max310x_gpio_set_config()
1284 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); in max310x_probe()
1287 return -ENOMEM; in max310x_probe()
1293 s->clk = clk_osc; in max310x_probe()
1297 s->clk = clk_xtal; in max310x_probe()
1301 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER || in max310x_probe()
1302 PTR_ERR(clk_xtal) == -EPROBE_DEFER) { in max310x_probe()
1303 return -EPROBE_DEFER; in max310x_probe()
1306 return -EINVAL; in max310x_probe()
1309 ret = clk_prepare_enable(s->clk); in max310x_probe()
1313 freq = clk_get_rate(s->clk); in max310x_probe()
1316 ret = -ERANGE; in max310x_probe()
1320 s->regmap = regmap; in max310x_probe()
1321 s->devtype = devtype; in max310x_probe()
1325 ret = devtype->detect(dev); in max310x_probe()
1329 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1333 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, in max310x_probe()
1336 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0); in max310x_probe()
1340 regmap_read(s->regmap, in max310x_probe()
1344 regmap_write(s->regmap, MAX310X_MODE1_REG + offs, in max310x_probe()
1345 devtype->mode1); in max310x_probe()
1351 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1356 ret = -ERANGE; in max310x_probe()
1361 s->p[i].port.line = line; in max310x_probe()
1362 s->p[i].port.dev = dev; in max310x_probe()
1363 s->p[i].port.irq = irq; in max310x_probe()
1364 s->p[i].port.type = PORT_MAX310X; in max310x_probe()
1365 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; in max310x_probe()
1366 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; in max310x_probe()
1367 s->p[i].port.iotype = UPIO_PORT; in max310x_probe()
1368 s->p[i].port.iobase = i * 0x20; in max310x_probe()
1369 s->p[i].port.membase = (void __iomem *)~0; in max310x_probe()
1370 s->p[i].port.uartclk = uartclk; in max310x_probe()
1371 s->p[i].port.rs485_config = max310x_rs485_config; in max310x_probe()
1372 s->p[i].port.ops = &max310x_ops; in max310x_probe()
1374 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); in max310x_probe()
1376 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); in max310x_probe()
1378 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); in max310x_probe()
1380 INIT_WORK(&s->p[i].md_work, max310x_md_proc); in max310x_probe()
1382 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); in max310x_probe()
1383 /* Initialize SPI-transfer buffers */ in max310x_probe()
1384 s->p[i].wr_header = (s->p[i].port.iobase + MAX310X_THR_REG) | in max310x_probe()
1386 s->p[i].rd_header = (s->p[i].port.iobase + MAX310X_RHR_REG); in max310x_probe()
1389 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); in max310x_probe()
1391 s->p[i].port.dev = NULL; in max310x_probe()
1397 devtype->power(&s->p[i].port, 0); in max310x_probe()
1402 s->gpio.owner = THIS_MODULE; in max310x_probe()
1403 s->gpio.parent = dev; in max310x_probe()
1404 s->gpio.label = devtype->name; in max310x_probe()
1405 s->gpio.direction_input = max310x_gpio_direction_input; in max310x_probe()
1406 s->gpio.get = max310x_gpio_get; in max310x_probe()
1407 s->gpio.direction_output= max310x_gpio_direction_output; in max310x_probe()
1408 s->gpio.set = max310x_gpio_set; in max310x_probe()
1409 s->gpio.set_config = max310x_gpio_set_config; in max310x_probe()
1410 s->gpio.base = -1; in max310x_probe()
1411 s->gpio.ngpio = devtype->nr * 4; in max310x_probe()
1412 s->gpio.can_sleep = 1; in max310x_probe()
1413 ret = devm_gpiochip_add_data(dev, &s->gpio, s); in max310x_probe()
1427 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1428 if (s->p[i].port.dev) { in max310x_probe()
1429 uart_remove_one_port(&max310x_uart, &s->p[i].port); in max310x_probe()
1430 clear_bit(s->p[i].port.line, max310x_lines); in max310x_probe()
1435 clk_disable_unprepare(s->clk); in max310x_probe()
1445 for (i = 0; i < s->devtype->nr; i++) { in max310x_remove()
1446 cancel_work_sync(&s->p[i].tx_work); in max310x_remove()
1447 cancel_work_sync(&s->p[i].md_work); in max310x_remove()
1448 cancel_work_sync(&s->p[i].rs_work); in max310x_remove()
1449 uart_remove_one_port(&max310x_uart, &s->p[i].port); in max310x_remove()
1450 clear_bit(s->p[i].port.line, max310x_lines); in max310x_remove()
1451 s->devtype->power(&s->p[i].port, 0); in max310x_remove()
1454 clk_disable_unprepare(s->clk); in max310x_remove()
1486 spi->bits_per_word = 8; in max310x_spi_probe()
1487 spi->mode = spi->mode ? : SPI_MODE_0; in max310x_spi_probe()
1488 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; in max310x_spi_probe()
1493 if (spi->dev.of_node) { in max310x_spi_probe()
1495 of_match_device(max310x_dt_ids, &spi->dev); in max310x_spi_probe()
1497 return -ENODEV; in max310x_spi_probe()
1499 devtype = (struct max310x_devtype *)of_id->data; in max310x_spi_probe()
1503 devtype = (struct max310x_devtype *)id_entry->driver_data; in max310x_spi_probe()
1506 regcfg.max_register = devtype->nr * 0x20 - 1; in max310x_spi_probe()
1509 return max310x_probe(&spi->dev, devtype, regmap, spi->irq); in max310x_spi_probe()
1514 return max310x_remove(&spi->dev); in max310x_spi_remove()