Lines Matching +full:auto +full:- +full:flow +full:- +full:control
1 // SPDX-License-Identifier: GPL-2.0+
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
32 readb(bd->re_map_membase + 0x8D); in neo_pci_posting_flush()
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
43 /* Turn on auto CTS flow control */ in neo_set_cts_flow_control()
47 /* Turn off auto Xon flow control */ in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
54 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); in neo_set_cts_flow_control()
60 writeb(8, &ch->ch_neo_uart->tfifo); in neo_set_cts_flow_control()
61 ch->ch_t_tlevel = 8; in neo_set_cts_flow_control()
63 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
69 ier = readb(&ch->ch_neo_uart->ier); in neo_set_rts_flow_control()
70 efr = readb(&ch->ch_neo_uart->efr); in neo_set_rts_flow_control()
72 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n"); in neo_set_rts_flow_control()
74 /* Turn on auto RTS flow control */ in neo_set_rts_flow_control()
78 /* Turn off auto Xoff flow control */ in neo_set_rts_flow_control()
83 writeb(0, &ch->ch_neo_uart->efr); in neo_set_rts_flow_control()
86 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_rts_flow_control()
88 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); in neo_set_rts_flow_control()
89 ch->ch_r_watermark = 4; in neo_set_rts_flow_control()
91 writeb(56, &ch->ch_neo_uart->rfifo); in neo_set_rts_flow_control()
92 ch->ch_r_tlevel = 56; in neo_set_rts_flow_control()
94 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_rts_flow_control()
98 * The auto RTS/DTR function must be started by asserting in neo_set_rts_flow_control()
99 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after in neo_set_rts_flow_control()
102 ch->ch_mostat |= (UART_MCR_RTS); in neo_set_rts_flow_control()
109 ier = readb(&ch->ch_neo_uart->ier); in neo_set_ixon_flow_control()
110 efr = readb(&ch->ch_neo_uart->efr); in neo_set_ixon_flow_control()
112 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n"); in neo_set_ixon_flow_control()
114 /* Turn off auto CTS flow control */ in neo_set_ixon_flow_control()
118 /* Turn on auto Xon flow control */ in neo_set_ixon_flow_control()
122 writeb(0, &ch->ch_neo_uart->efr); in neo_set_ixon_flow_control()
125 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_ixon_flow_control()
127 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); in neo_set_ixon_flow_control()
128 ch->ch_r_watermark = 4; in neo_set_ixon_flow_control()
130 writeb(32, &ch->ch_neo_uart->rfifo); in neo_set_ixon_flow_control()
131 ch->ch_r_tlevel = 32; in neo_set_ixon_flow_control()
134 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); in neo_set_ixon_flow_control()
135 writeb(0, &ch->ch_neo_uart->xonchar2); in neo_set_ixon_flow_control()
137 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); in neo_set_ixon_flow_control()
138 writeb(0, &ch->ch_neo_uart->xoffchar2); in neo_set_ixon_flow_control()
140 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_ixon_flow_control()
146 ier = readb(&ch->ch_neo_uart->ier); in neo_set_ixoff_flow_control()
147 efr = readb(&ch->ch_neo_uart->efr); in neo_set_ixoff_flow_control()
149 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n"); in neo_set_ixoff_flow_control()
151 /* Turn off auto RTS flow control */ in neo_set_ixoff_flow_control()
155 /* Turn on auto Xoff flow control */ in neo_set_ixoff_flow_control()
160 writeb(0, &ch->ch_neo_uart->efr); in neo_set_ixoff_flow_control()
163 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_ixoff_flow_control()
166 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); in neo_set_ixoff_flow_control()
168 writeb(8, &ch->ch_neo_uart->tfifo); in neo_set_ixoff_flow_control()
169 ch->ch_t_tlevel = 8; in neo_set_ixoff_flow_control()
172 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); in neo_set_ixoff_flow_control()
173 writeb(0, &ch->ch_neo_uart->xonchar2); in neo_set_ixoff_flow_control()
175 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); in neo_set_ixoff_flow_control()
176 writeb(0, &ch->ch_neo_uart->xoffchar2); in neo_set_ixoff_flow_control()
178 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_ixoff_flow_control()
184 ier = readb(&ch->ch_neo_uart->ier); in neo_set_no_input_flow_control()
185 efr = readb(&ch->ch_neo_uart->efr); in neo_set_no_input_flow_control()
187 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n"); in neo_set_no_input_flow_control()
189 /* Turn off auto RTS flow control */ in neo_set_no_input_flow_control()
193 /* Turn off auto Xoff flow control */ in neo_set_no_input_flow_control()
195 if (ch->ch_c_iflag & IXON) in neo_set_no_input_flow_control()
201 writeb(0, &ch->ch_neo_uart->efr); in neo_set_no_input_flow_control()
204 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_no_input_flow_control()
207 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); in neo_set_no_input_flow_control()
209 ch->ch_r_watermark = 0; in neo_set_no_input_flow_control()
211 writeb(16, &ch->ch_neo_uart->tfifo); in neo_set_no_input_flow_control()
212 ch->ch_t_tlevel = 16; in neo_set_no_input_flow_control()
214 writeb(16, &ch->ch_neo_uart->rfifo); in neo_set_no_input_flow_control()
215 ch->ch_r_tlevel = 16; in neo_set_no_input_flow_control()
217 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_no_input_flow_control()
223 ier = readb(&ch->ch_neo_uart->ier); in neo_set_no_output_flow_control()
224 efr = readb(&ch->ch_neo_uart->efr); in neo_set_no_output_flow_control()
226 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n"); in neo_set_no_output_flow_control()
228 /* Turn off auto CTS flow control */ in neo_set_no_output_flow_control()
232 /* Turn off auto Xon flow control */ in neo_set_no_output_flow_control()
233 if (ch->ch_c_iflag & IXOFF) in neo_set_no_output_flow_control()
239 writeb(0, &ch->ch_neo_uart->efr); in neo_set_no_output_flow_control()
242 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_no_output_flow_control()
245 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr); in neo_set_no_output_flow_control()
247 ch->ch_r_watermark = 0; in neo_set_no_output_flow_control()
249 writeb(16, &ch->ch_neo_uart->tfifo); in neo_set_no_output_flow_control()
250 ch->ch_t_tlevel = 16; in neo_set_no_output_flow_control()
252 writeb(16, &ch->ch_neo_uart->rfifo); in neo_set_no_output_flow_control()
253 ch->ch_r_tlevel = 16; in neo_set_no_output_flow_control()
255 writeb(ier, &ch->ch_neo_uart->ier); in neo_set_no_output_flow_control()
261 /* if hardware flow control is set, then skip this whole thing */ in neo_set_new_start_stop_chars()
262 if (ch->ch_c_cflag & CRTSCTS) in neo_set_new_start_stop_chars()
265 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n"); in neo_set_new_start_stop_chars()
268 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1); in neo_set_new_start_stop_chars()
269 writeb(0, &ch->ch_neo_uart->xonchar2); in neo_set_new_start_stop_chars()
271 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1); in neo_set_new_start_stop_chars()
272 writeb(0, &ch->ch_neo_uart->xoffchar2); in neo_set_new_start_stop_chars()
286 head = ch->ch_r_head & RQUEUEMASK; in neo_copy_data_from_uart_to_queue()
287 tail = ch->ch_r_tail & RQUEUEMASK; in neo_copy_data_from_uart_to_queue()
290 linestatus = ch->ch_cached_lsr; in neo_copy_data_from_uart_to_queue()
291 ch->ch_cached_lsr = 0; in neo_copy_data_from_uart_to_queue()
294 if ((qleft = tail - head - 1) < 0) in neo_copy_data_from_uart_to_queue()
304 if (!(ch->ch_flags & CH_FIFO_ENABLED)) in neo_copy_data_from_uart_to_queue()
307 total = readb(&ch->ch_neo_uart->rfifo); in neo_copy_data_from_uart_to_queue()
310 * EXAR chip bug - RX FIFO COUNT - Fudge factor. in neo_copy_data_from_uart_to_queue()
314 * The count can be any where from 0-3 bytes "off". in neo_copy_data_from_uart_to_queue()
317 total -= 3; in neo_copy_data_from_uart_to_queue()
333 linestatus = readb(&ch->ch_neo_uart->lsr); in neo_copy_data_from_uart_to_queue()
344 n = min(((u32) total), (RQUEUESIZE - (u32) head)); in neo_copy_data_from_uart_to_queue()
360 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_copy_data_from_uart_to_queue()
365 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n); in neo_copy_data_from_uart_to_queue()
371 memset(ch->ch_equeue + head, 0, n); in neo_copy_data_from_uart_to_queue()
375 total -= n; in neo_copy_data_from_uart_to_queue()
376 qleft -= n; in neo_copy_data_from_uart_to_queue()
377 ch->ch_rxcount += n; in neo_copy_data_from_uart_to_queue()
384 if (ch->ch_c_iflag & IGNBRK) in neo_copy_data_from_uart_to_queue()
397 linestatus |= readb(&ch->ch_neo_uart->lsr); in neo_copy_data_from_uart_to_queue()
405 ch->ch_cached_lsr = linestatus; in neo_copy_data_from_uart_to_queue()
419 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_copy_data_from_uart_to_queue()
428 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1); in neo_copy_data_from_uart_to_queue()
441 jsm_dbg(READ, &ch->ch_bd->pci_dev, in neo_copy_data_from_uart_to_queue()
443 ch->ch_rqueue[tail], ch->ch_equeue[tail]); in neo_copy_data_from_uart_to_queue()
445 ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK; in neo_copy_data_from_uart_to_queue()
446 ch->ch_err_overrun++; in neo_copy_data_from_uart_to_queue()
450 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1); in neo_copy_data_from_uart_to_queue()
451 ch->ch_equeue[head] = (u8) linestatus; in neo_copy_data_from_uart_to_queue()
453 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n", in neo_copy_data_from_uart_to_queue()
454 ch->ch_rqueue[head], ch->ch_equeue[head]); in neo_copy_data_from_uart_to_queue()
462 qleft--; in neo_copy_data_from_uart_to_queue()
463 ch->ch_rxcount++; in neo_copy_data_from_uart_to_queue()
469 ch->ch_r_head = head & RQUEUEMASK; in neo_copy_data_from_uart_to_queue()
470 ch->ch_e_head = head & EQUEUEMASK; in neo_copy_data_from_uart_to_queue()
487 circ = &ch->uart_port.state->xmit; in neo_copy_data_from_queue_to_uart()
494 if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) in neo_copy_data_from_queue_to_uart()
499 if (!(ch->ch_flags & CH_FIFO_ENABLED)) { in neo_copy_data_from_queue_to_uart()
500 u8 lsrbits = readb(&ch->ch_neo_uart->lsr); in neo_copy_data_from_queue_to_uart()
502 ch->ch_cached_lsr |= lsrbits; in neo_copy_data_from_queue_to_uart()
503 if (ch->ch_cached_lsr & UART_LSR_THRE) { in neo_copy_data_from_queue_to_uart()
504 ch->ch_cached_lsr &= ~(UART_LSR_THRE); in neo_copy_data_from_queue_to_uart()
506 writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx); in neo_copy_data_from_queue_to_uart()
507 jsm_dbg(WRITE, &ch->ch_bd->pci_dev, in neo_copy_data_from_queue_to_uart()
508 "Tx data: %x\n", circ->buf[circ->tail]); in neo_copy_data_from_queue_to_uart()
509 circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1); in neo_copy_data_from_queue_to_uart()
510 ch->ch_txcount++; in neo_copy_data_from_queue_to_uart()
518 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) in neo_copy_data_from_queue_to_uart()
521 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel; in neo_copy_data_from_queue_to_uart()
524 head = circ->head & (UART_XMIT_SIZE - 1); in neo_copy_data_from_queue_to_uart()
525 tail = circ->tail & (UART_XMIT_SIZE - 1); in neo_copy_data_from_queue_to_uart()
533 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail; in neo_copy_data_from_queue_to_uart()
539 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s); in neo_copy_data_from_queue_to_uart()
541 tail = (tail + s) & (UART_XMIT_SIZE - 1); in neo_copy_data_from_queue_to_uart()
542 n -= s; in neo_copy_data_from_queue_to_uart()
543 ch->ch_txcount += s; in neo_copy_data_from_queue_to_uart()
548 circ->tail = tail & (UART_XMIT_SIZE - 1); in neo_copy_data_from_queue_to_uart()
550 if (len_written >= ch->ch_t_tlevel) in neo_copy_data_from_queue_to_uart()
551 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_copy_data_from_queue_to_uart()
554 uart_write_wakeup(&ch->uart_port); in neo_copy_data_from_queue_to_uart()
561 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, in neo_parse_modem()
563 ch->ch_portnum, msignals); in neo_parse_modem()
570 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD); in neo_parse_modem()
572 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS); in neo_parse_modem()
574 ch->ch_mistat |= UART_MSR_DCD; in neo_parse_modem()
576 ch->ch_mistat &= ~UART_MSR_DCD; in neo_parse_modem()
579 ch->ch_mistat |= UART_MSR_DSR; in neo_parse_modem()
581 ch->ch_mistat &= ~UART_MSR_DSR; in neo_parse_modem()
584 ch->ch_mistat |= UART_MSR_RI; in neo_parse_modem()
586 ch->ch_mistat &= ~UART_MSR_RI; in neo_parse_modem()
589 ch->ch_mistat |= UART_MSR_CTS; in neo_parse_modem()
591 ch->ch_mistat &= ~UART_MSR_CTS; in neo_parse_modem()
593 jsm_dbg(MSIGS, &ch->ch_bd->pci_dev, in neo_parse_modem()
595 ch->ch_portnum, in neo_parse_modem()
596 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR), in neo_parse_modem()
597 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS), in neo_parse_modem()
598 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS), in neo_parse_modem()
599 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR), in neo_parse_modem()
600 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI), in neo_parse_modem()
601 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD)); in neo_parse_modem()
610 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); in neo_assert_modem_signals()
613 neo_pci_posting_flush(ch->ch_bd); in neo_assert_modem_signals()
629 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); in neo_flush_uart_write()
634 tmp = readb(&ch->ch_neo_uart->isr_fcr); in neo_flush_uart_write()
636 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in neo_flush_uart_write()
644 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_flush_uart_write()
661 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr); in neo_flush_uart_read()
666 tmp = readb(&ch->ch_neo_uart->isr_fcr); in neo_flush_uart_read()
668 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in neo_flush_uart_read()
684 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_clear_break()
687 if (ch->ch_flags & CH_BREAK_SENDING) { in neo_clear_break()
688 u8 temp = readb(&ch->ch_neo_uart->lcr); in neo_clear_break()
689 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr); in neo_clear_break()
691 ch->ch_flags &= ~(CH_BREAK_SENDING); in neo_clear_break()
692 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev, in neo_clear_break()
697 neo_pci_posting_flush(ch->ch_bd); in neo_clear_break()
699 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_clear_break()
715 if (port >= brd->maxports) in neo_parse_isr()
718 ch = brd->channels[port]; in neo_parse_isr()
725 isr = readb(&ch->ch_neo_uart->isr_fcr); in neo_parse_isr()
736 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n", in neo_parse_isr()
740 /* Read data from uart -> queue */ in neo_parse_isr()
743 /* Call our tty layer to enforce queue flow control if needed. */ in neo_parse_isr()
744 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_isr()
746 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_isr()
750 /* Transfer data (if any) from Write Queue -> UART. */ in neo_parse_isr()
751 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_isr()
752 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_parse_isr()
753 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_isr()
758 cause = readb(&ch->ch_neo_uart->xoffchar1); in neo_parse_isr()
760 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
767 * one it was, so we can suspend or resume data flow. in neo_parse_isr()
769 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_isr()
772 if (brd->channels[port]->ch_flags & CH_STOP) { in neo_parse_isr()
773 ch->ch_flags &= ~(CH_STOP); in neo_parse_isr()
775 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
780 if (!(brd->channels[port]->ch_flags & CH_STOP)) { in neo_parse_isr()
781 ch->ch_flags |= CH_STOP; in neo_parse_isr()
782 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
785 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
789 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_isr()
794 * If we get here, this means the hardware is doing auto flow control. in neo_parse_isr()
797 cause = readb(&ch->ch_neo_uart->mcr); in neo_parse_isr()
799 /* Which pin is doing auto flow? RTS or DTR? */ in neo_parse_isr()
800 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_isr()
803 ch->ch_mostat |= UART_MCR_RTS; in neo_parse_isr()
805 ch->ch_mostat &= ~(UART_MCR_RTS); in neo_parse_isr()
808 ch->ch_mostat |= UART_MCR_DTR; in neo_parse_isr()
810 ch->ch_mostat &= ~(UART_MCR_DTR); in neo_parse_isr()
812 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_isr()
816 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_isr()
818 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); in neo_parse_isr()
831 if (port >= brd->maxports) in neo_parse_lsr()
834 ch = brd->channels[port]; in neo_parse_lsr()
838 linestatus = readb(&ch->ch_neo_uart->lsr); in neo_parse_lsr()
840 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n", in neo_parse_lsr()
843 ch->ch_cached_lsr |= linestatus; in neo_parse_lsr()
845 if (ch->ch_cached_lsr & UART_LSR_DR) { in neo_parse_lsr()
846 /* Read data from uart -> queue */ in neo_parse_lsr()
848 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_lsr()
850 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_lsr()
860 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_lsr()
870 ch->ch_err_parity++; in neo_parse_lsr()
871 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n", in neo_parse_lsr()
876 ch->ch_err_frame++; in neo_parse_lsr()
877 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n", in neo_parse_lsr()
882 ch->ch_err_break++; in neo_parse_lsr()
883 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_lsr()
895 ch->ch_err_overrun++; in neo_parse_lsr()
896 jsm_dbg(INTR, &ch->ch_bd->pci_dev, in neo_parse_lsr()
902 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_lsr()
903 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_parse_lsr()
904 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_lsr()
906 /* Transfer data (if any) from Write Queue -> UART. */ in neo_parse_lsr()
910 spin_lock_irqsave(&ch->ch_lock, lock_flags); in neo_parse_lsr()
911 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_parse_lsr()
912 spin_unlock_irqrestore(&ch->ch_lock, lock_flags); in neo_parse_lsr()
914 /* Transfer data (if any) from Write Queue -> UART. */ in neo_parse_lsr()
931 bd = ch->ch_bd; in neo_param()
938 if ((ch->ch_c_cflag & (CBAUD)) == 0) { in neo_param()
939 ch->ch_r_head = ch->ch_r_tail = 0; in neo_param()
940 ch->ch_e_head = ch->ch_e_tail = 0; in neo_param()
945 ch->ch_flags |= (CH_BAUD0); in neo_param()
946 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR); in neo_param()
978 cflag = C_BAUD(ch->uart_port.state->port.tty); in neo_param()
987 if (ch->ch_flags & CH_BAUD0) in neo_param()
988 ch->ch_flags &= ~(CH_BAUD0); in neo_param()
991 if (ch->ch_c_cflag & PARENB) in neo_param()
994 if (!(ch->ch_c_cflag & PARODD)) in neo_param()
1002 if (ch->ch_c_cflag & CMSPAR) in neo_param()
1006 if (ch->ch_c_cflag & CSTOPB) in neo_param()
1009 switch (ch->ch_c_cflag & CSIZE) { in neo_param()
1025 ier = readb(&ch->ch_neo_uart->ier); in neo_param()
1026 uart_lcr = readb(&ch->ch_neo_uart->lcr); in neo_param()
1028 quot = ch->ch_bd->bd_dividend / baud; in neo_param()
1031 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr); in neo_param()
1032 writeb((quot & 0xff), &ch->ch_neo_uart->txrx); in neo_param()
1033 writeb((quot >> 8), &ch->ch_neo_uart->ier); in neo_param()
1034 writeb(lcr, &ch->ch_neo_uart->lcr); in neo_param()
1038 writeb(lcr, &ch->ch_neo_uart->lcr); in neo_param()
1040 if (ch->ch_c_cflag & CREAD) in neo_param()
1045 writeb(ier, &ch->ch_neo_uart->ier); in neo_param()
1050 if (ch->ch_c_cflag & CRTSCTS) in neo_param()
1052 else if (ch->ch_c_iflag & IXON) { in neo_param()
1053 /* If start/stop is set to disable, then we should disable flow control */ in neo_param()
1054 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) in neo_param()
1062 if (ch->ch_c_cflag & CRTSCTS) in neo_param()
1064 else if (ch->ch_c_iflag & IXOFF) { in neo_param()
1065 /* If start/stop is set to disable, then we should disable flow control */ in neo_param()
1066 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR)) in neo_param()
1079 writeb(1, &ch->ch_neo_uart->rfifo); in neo_param()
1080 ch->ch_r_tlevel = 1; in neo_param()
1086 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); in neo_param()
1109 spin_lock_irqsave(&brd->bd_intr_lock, lock_flags); in neo_intr()
1113 * Bits 0-7: What port triggered the interrupt. in neo_intr()
1114 * Bits 8-31: Each 3bits indicate what type of interrupt occurred. in neo_intr()
1116 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET); in neo_intr()
1118 jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n", in neo_intr()
1122 jsm_dbg(INTR, &brd->pci_dev, in neo_intr()
1124 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); in neo_intr()
1148 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n", in neo_intr()
1156 jsm_dbg(INTR, &brd->pci_dev, in neo_intr()
1166 * RXRDY Time-out is cleared by reading data in the in neo_intr()
1171 if (port >= brd->nasync) in neo_intr()
1174 ch = brd->channels[port]; in neo_intr()
1180 /* Call our tty layer to enforce queue flow control if needed. */ in neo_intr()
1181 spin_lock_irqsave(&ch->ch_lock, lock_flags2); in neo_intr()
1183 spin_unlock_irqrestore(&ch->ch_lock, lock_flags2); in neo_intr()
1212 * MSR or flow control was seen. in neo_intr()
1224 jsm_dbg(INTR, &brd->pci_dev, in neo_intr()
1231 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags); in neo_intr()
1233 jsm_dbg(INTR, &brd->pci_dev, "finish\n"); in neo_intr()
1239 * Used as a way to enforce queue flow control when in
1240 * hardware flow control mode.
1244 u8 tmp = readb(&ch->ch_neo_uart->ier); in neo_disable_receiver()
1246 writeb(tmp, &ch->ch_neo_uart->ier); in neo_disable_receiver()
1249 neo_pci_posting_flush(ch->ch_bd); in neo_disable_receiver()
1255 * Used as a way to un-enforce queue flow control when in
1256 * hardware flow control mode.
1260 u8 tmp = readb(&ch->ch_neo_uart->ier); in neo_enable_receiver()
1262 writeb(tmp, &ch->ch_neo_uart->ier); in neo_enable_receiver()
1265 neo_pci_posting_flush(ch->ch_bd); in neo_enable_receiver()
1273 if (ch->ch_startc != __DISABLED_CHAR) { in neo_send_start_character()
1274 ch->ch_xon_sends++; in neo_send_start_character()
1275 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx); in neo_send_start_character()
1278 neo_pci_posting_flush(ch->ch_bd); in neo_send_start_character()
1287 if (ch->ch_stopc != __DISABLED_CHAR) { in neo_send_stop_character()
1288 ch->ch_xoff_sends++; in neo_send_stop_character()
1289 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx); in neo_send_stop_character()
1292 neo_pci_posting_flush(ch->ch_bd); in neo_send_stop_character()
1301 writeb(0, &ch->ch_neo_uart->ier); in neo_uart_init()
1302 writeb(0, &ch->ch_neo_uart->efr); in neo_uart_init()
1303 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr); in neo_uart_init()
1306 readb(&ch->ch_neo_uart->txrx); in neo_uart_init()
1307 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr); in neo_uart_init()
1308 readb(&ch->ch_neo_uart->lsr); in neo_uart_init()
1309 readb(&ch->ch_neo_uart->msr); in neo_uart_init()
1311 ch->ch_flags |= CH_FIFO_ENABLED; in neo_uart_init()
1314 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); in neo_uart_init()
1323 writeb(0, &ch->ch_neo_uart->efr); in neo_uart_off()
1326 writeb(0, &ch->ch_neo_uart->ier); in neo_uart_off()
1332 u8 lsr = readb(&ch->ch_neo_uart->lsr); in neo_get_uart_bytes_left()
1335 ch->ch_cached_lsr |= lsr; in neo_get_uart_bytes_left()
1341 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM); in neo_get_uart_bytes_left()
1358 if (!(ch->ch_flags & CH_BREAK_SENDING)) { in neo_send_break()
1359 u8 temp = readb(&ch->ch_neo_uart->lcr); in neo_send_break()
1360 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr); in neo_send_break()
1361 ch->ch_flags |= (CH_BREAK_SENDING); in neo_send_break()
1364 neo_pci_posting_flush(ch->ch_bd); in neo_send_break()
1381 writeb(c, &ch->ch_neo_uart->txrx); in neo_send_immediate_char()
1384 neo_pci_posting_flush(ch->ch_bd); in neo_send_immediate_char()