Lines Matching +full:rx +full:- +full:enable
1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
65 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
71 #define EXT_INT_ENAB 0x1 /* Ext Int Enable */
72 #define TxINT_ENAB 0x2 /* Tx Int Enable */
75 #define RxINT_DISAB 0 /* Rx Int Disable */
76 #define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
77 #define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
83 #define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
89 #define RxENAB 0x1 /* Rx Enable */
92 #define RxCRC_ENAB 0x8 /* Rx CRC Enable */
95 #define Rx5 0x0 /* Rx 5 Bits/Character */
96 #define Rx7 0x40 /* Rx 7 Bits/Character */
97 #define Rx6 0x80 /* Rx 6 Bits/Character */
98 #define Rx8 0xc0 /* Rx 8 Bits/Character */
103 #define PAR_ENAB 0x1 /* Parity Enable */
106 #define SYNC_ENAB 0 /* Sync Modes Enable */
124 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
127 #define TxENAB 0x8 /* Tx Enable */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
146 #define MIE 8 /* Master Interrupt Enable */
186 #define BRENAB 1 /* Baud rate generator enable */
209 #define Rx_CH_AV 0x1 /* Rx Character Available */
220 /* Residue Data for 8 Rx bits/char programmed */
229 /* Special Rx Condition Interrupts */
231 #define Rx_OVR 0x20 /* Rx Overrun Error */
235 /* Read Register 2 (channel b only) - Interrupt vector */
249 #define CHBRxIP 0x4 /* Channel B Rx IP */
252 #define CHARxIP 0x20 /* Channel A Rx IP */
269 #define ZS_CLEARERR(channel) do { writeb(ERR_RES, &channel->control); \
272 #define ZS_CLEARSTAT(channel) do { writeb(RES_EXT_INT, &channel->control); \
275 #define ZS_CLEARFIFO(channel) do { readb(&channel->data); \
277 readb(&channel->data); \
279 readb(&channel->data); \