Lines Matching +full:misc +full:- +full:latch
1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
67 #define RES_EOM_L 0xC0 /* Reset EOM latch */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
153 /* Write Register 10 (misc control bits) */
185 /* Write Register 14 (Misc control bits) */
235 /* Read Register 2 (channel b only) - Interrupt vector */
256 /* Read Register 10 (misc status bits) */
268 /* Misc macros */
269 #define ZS_CLEARERR(channel) do { writeb(ERR_RES, &channel->control); \
272 #define ZS_CLEARSTAT(channel) do { writeb(RES_EXT_INT, &channel->control); \
275 #define ZS_CLEARFIFO(channel) do { readb(&channel->data); \
277 readb(&channel->data); \
279 readb(&channel->data); \