Lines Matching +full:8 +full:- +full:channel
1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
47 #define R8 8
98 #define Rx8 0xc0 /* Rx 8 Bits/Character */
111 #define MONSYNC 0 /* 8 Bit Sync character */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
132 #define Tx8 0x60 /* Tx 8 bits/character */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
140 /* Write Register 8 (transmit buffer) */
146 #define MIE 8 /* Master Interrupt Enable */
149 #define CHRB 0x40 /* Reset channel B */
150 #define CHRA 0x80 /* Reset channel A */
154 #define BIT6 1 /* 6 bit/8bit sync */
157 #define MARKIDLE 8 /* Mark/flag on idle */
172 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
189 #define AUTOECHO 8 /* Auto Echo */
201 #define DCDIE 8 /* DCD IE */
220 /* Residue Data for 8 Rx bits/char programmed */
226 #define RES8 0x6 /* 0/8 */
227 #define RES18 0xe /* 1/8 */
228 #define RES28 0x0 /* 2/8 */
235 /* Read Register 2 (channel b only) - Interrupt vector */
247 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
248 #define CHBTxIP 0x2 /* Channel B Tx IP */
249 #define CHBRxIP 0x4 /* Channel B Rx IP */
250 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
251 #define CHATxIP 0x10 /* Channel A Tx IP */
252 #define CHARxIP 0x20 /* Channel A Rx IP */
254 /* Read Register 8 (receive data register) */
269 #define ZS_CLEARERR(channel) do { writeb(ERR_RES, &channel->control); \ argument
272 #define ZS_CLEARSTAT(channel) do { writeb(RES_EXT_INT, &channel->control); \ argument
275 #define ZS_CLEARFIFO(channel) do { readb(&channel->data); \ argument
277 readb(&channel->data); \
279 readb(&channel->data); \