Lines Matching refs:sport
294 static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) in imx_uart_writel() argument
298 sport->ucr1 = val; in imx_uart_writel()
301 sport->ucr2 = val; in imx_uart_writel()
304 sport->ucr3 = val; in imx_uart_writel()
307 sport->ucr4 = val; in imx_uart_writel()
310 sport->ufcr = val; in imx_uart_writel()
315 writel(val, sport->port.membase + offset); in imx_uart_writel()
318 static u32 imx_uart_readl(struct imx_port *sport, u32 offset) in imx_uart_readl() argument
322 return sport->ucr1; in imx_uart_readl()
331 if (!(sport->ucr2 & UCR2_SRST)) in imx_uart_readl()
332 sport->ucr2 = readl(sport->port.membase + offset); in imx_uart_readl()
333 return sport->ucr2; in imx_uart_readl()
336 return sport->ucr3; in imx_uart_readl()
339 return sport->ucr4; in imx_uart_readl()
342 return sport->ufcr; in imx_uart_readl()
345 return readl(sport->port.membase + offset); in imx_uart_readl()
349 static inline unsigned imx_uart_uts_reg(struct imx_port *sport) in imx_uart_uts_reg() argument
351 return sport->devdata->uts_reg; in imx_uart_uts_reg()
354 static inline int imx_uart_is_imx1(struct imx_port *sport) in imx_uart_is_imx1() argument
356 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
359 static inline int imx_uart_is_imx21(struct imx_port *sport) in imx_uart_is_imx21() argument
361 return sport->devdata->devtype == IMX21_UART; in imx_uart_is_imx21()
364 static inline int imx_uart_is_imx53(struct imx_port *sport) in imx_uart_is_imx53() argument
366 return sport->devdata->devtype == IMX53_UART; in imx_uart_is_imx53()
369 static inline int imx_uart_is_imx6q(struct imx_port *sport) in imx_uart_is_imx6q() argument
371 return sport->devdata->devtype == IMX6Q_UART; in imx_uart_is_imx6q()
377 static void imx_uart_ucrs_save(struct imx_port *sport, in imx_uart_ucrs_save() argument
381 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
382 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
383 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
386 static void imx_uart_ucrs_restore(struct imx_port *sport, in imx_uart_ucrs_restore() argument
390 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
391 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
392 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
397 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2) in imx_uart_rts_active() argument
401 sport->port.mctrl |= TIOCM_RTS; in imx_uart_rts_active()
402 mctrl_gpio_set(sport->gpios, sport->port.mctrl); in imx_uart_rts_active()
406 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2) in imx_uart_rts_inactive() argument
411 sport->port.mctrl &= ~TIOCM_RTS; in imx_uart_rts_inactive()
412 mctrl_gpio_set(sport->gpios, sport->port.mctrl); in imx_uart_rts_inactive()
427 struct imx_port *sport = (struct imx_port *)port; in imx_uart_start_rx() local
430 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_start_rx()
431 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_start_rx()
435 if (sport->dma_is_enabled) { in imx_uart_start_rx()
443 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_start_rx()
444 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_start_rx()
450 struct imx_port *sport = (struct imx_port *)port; in imx_uart_stop_tx() local
453 if (sport->tx_state == OFF) in imx_uart_stop_tx()
460 if (sport->dma_is_txing) in imx_uart_stop_tx()
463 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_stop_tx()
464 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1); in imx_uart_stop_tx()
466 usr2 = imx_uart_readl(sport, USR2); in imx_uart_stop_tx()
472 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_stop_tx()
474 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_stop_tx()
478 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
479 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
480 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
485 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
486 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
489 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
491 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_stop_tx()
493 imx_uart_rts_active(sport, &ucr2); in imx_uart_stop_tx()
495 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_stop_tx()
496 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_stop_tx()
500 sport->tx_state = OFF; in imx_uart_stop_tx()
503 sport->tx_state = OFF; in imx_uart_stop_tx()
510 struct imx_port *sport = (struct imx_port *)port; in imx_uart_stop_rx() local
513 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_stop_rx()
514 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_stop_rx()
516 if (sport->dma_is_enabled) { in imx_uart_stop_rx()
522 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_stop_rx()
525 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_stop_rx()
531 struct imx_port *sport = (struct imx_port *)port; in imx_uart_enable_ms() local
533 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
535 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
538 static void imx_uart_dma_tx(struct imx_port *sport);
541 static inline void imx_uart_transmit_buffer(struct imx_port *sport) in imx_uart_transmit_buffer() argument
543 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_transmit_buffer()
545 if (sport->port.x_char) { in imx_uart_transmit_buffer()
547 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
548 sport->port.icount.tx++; in imx_uart_transmit_buffer()
549 sport->port.x_char = 0; in imx_uart_transmit_buffer()
553 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
554 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
558 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
564 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_transmit_buffer()
566 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
568 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_transmit_buffer()
570 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_transmit_buffer()
571 imx_uart_dma_tx(sport); in imx_uart_transmit_buffer()
578 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) { in imx_uart_transmit_buffer()
581 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); in imx_uart_transmit_buffer()
583 sport->port.icount.tx++; in imx_uart_transmit_buffer()
587 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
590 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
595 struct imx_port *sport = data; in imx_uart_dma_tx_callback() local
596 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
597 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx_callback()
601 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
603 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
605 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_dma_tx_callback()
607 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_dma_tx_callback()
610 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); in imx_uart_dma_tx_callback()
611 sport->port.icount.tx += sport->tx_bytes; in imx_uart_dma_tx_callback()
613 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
615 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
618 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
620 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
621 imx_uart_dma_tx(sport); in imx_uart_dma_tx_callback()
622 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
623 u32 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_dma_tx_callback()
625 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_dma_tx_callback()
628 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
632 static void imx_uart_dma_tx(struct imx_port *sport) in imx_uart_dma_tx() argument
634 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx()
635 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
637 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
638 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
642 if (sport->dma_is_txing) in imx_uart_dma_tx()
645 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_dma_tx()
647 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_dma_tx()
649 sport->tx_bytes = uart_circ_chars_pending(xmit); in imx_uart_dma_tx()
652 sport->dma_tx_nents = 1; in imx_uart_dma_tx()
653 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); in imx_uart_dma_tx()
655 sport->dma_tx_nents = 2; in imx_uart_dma_tx()
662 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
670 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
676 desc->callback_param = sport; in imx_uart_dma_tx()
681 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_dma_tx()
683 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_dma_tx()
686 sport->dma_is_txing = 1; in imx_uart_dma_tx()
695 struct imx_port *sport = (struct imx_port *)port; in imx_uart_start_tx() local
698 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) in imx_uart_start_tx()
708 if (sport->tx_state == OFF) { in imx_uart_start_tx()
709 u32 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_start_tx()
711 imx_uart_rts_active(sport, &ucr2); in imx_uart_start_tx()
713 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_start_tx()
714 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_start_tx()
719 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
720 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
725 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
726 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
728 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
735 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
736 u32 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_start_tx()
738 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_start_tx()
741 sport->tx_state = SEND; in imx_uart_start_tx()
744 sport->tx_state = SEND; in imx_uart_start_tx()
747 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
748 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_start_tx()
749 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1); in imx_uart_start_tx()
752 if (sport->dma_is_enabled) { in imx_uart_start_tx()
753 if (sport->port.x_char) { in imx_uart_start_tx()
756 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_start_tx()
759 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_start_tx()
765 imx_uart_dma_tx(sport); in imx_uart_start_tx()
772 struct imx_port *sport = dev_id; in __imx_uart_rtsint() local
775 imx_uart_writel(sport, USR1_RTSD, USR1); in __imx_uart_rtsint()
776 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS; in __imx_uart_rtsint()
777 uart_handle_cts_change(&sport->port, !!usr1); in __imx_uart_rtsint()
778 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
785 struct imx_port *sport = dev_id; in imx_uart_rtsint() local
788 spin_lock(&sport->port.lock); in imx_uart_rtsint()
792 spin_unlock(&sport->port.lock); in imx_uart_rtsint()
799 struct imx_port *sport = dev_id; in imx_uart_txint() local
801 spin_lock(&sport->port.lock); in imx_uart_txint()
802 imx_uart_transmit_buffer(sport); in imx_uart_txint()
803 spin_unlock(&sport->port.lock); in imx_uart_txint()
809 struct imx_port *sport = dev_id; in __imx_uart_rxint() local
811 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
813 while (imx_uart_readl(sport, USR2) & USR2_RDR) { in __imx_uart_rxint()
817 sport->port.icount.rx++; in __imx_uart_rxint()
819 rx = imx_uart_readl(sport, URXD0); in __imx_uart_rxint()
821 usr2 = imx_uart_readl(sport, USR2); in __imx_uart_rxint()
823 imx_uart_writel(sport, USR2_BRCD, USR2); in __imx_uart_rxint()
824 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
828 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in __imx_uart_rxint()
833 sport->port.icount.brk++; in __imx_uart_rxint()
835 sport->port.icount.parity++; in __imx_uart_rxint()
837 sport->port.icount.frame++; in __imx_uart_rxint()
839 sport->port.icount.overrun++; in __imx_uart_rxint()
841 if (rx & sport->port.ignore_status_mask) { in __imx_uart_rxint()
847 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
858 sport->port.sysrq = 0; in __imx_uart_rxint()
861 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
865 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
876 struct imx_port *sport = dev_id; in imx_uart_rxint() local
879 spin_lock(&sport->port.lock); in imx_uart_rxint()
883 spin_unlock(&sport->port.lock); in imx_uart_rxint()
888 static void imx_uart_clear_rx_errors(struct imx_port *sport);
893 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport) in imx_uart_get_hwmctrl() argument
896 unsigned usr1 = imx_uart_readl(sport, USR1); in imx_uart_get_hwmctrl()
897 unsigned usr2 = imx_uart_readl(sport, USR2); in imx_uart_get_hwmctrl()
906 if (sport->dte_mode) in imx_uart_get_hwmctrl()
907 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN)) in imx_uart_get_hwmctrl()
916 static void imx_uart_mctrl_check(struct imx_port *sport) in imx_uart_mctrl_check() argument
920 status = imx_uart_get_hwmctrl(sport); in imx_uart_mctrl_check()
921 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
926 sport->old_status = status; in imx_uart_mctrl_check()
929 sport->port.icount.rng++; in imx_uart_mctrl_check()
931 sport->port.icount.dsr++; in imx_uart_mctrl_check()
933 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
935 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
937 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
942 struct imx_port *sport = dev_id; in imx_uart_int() local
952 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_int()
954 usr1 = imx_uart_readl(sport, USR1); in imx_uart_int()
955 usr2 = imx_uart_readl(sport, USR2); in imx_uart_int()
956 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_int()
957 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_int()
958 ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_int()
959 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_int()
987 imx_uart_writel(sport, USR1_AGTIM, USR1); in imx_uart_int()
994 imx_uart_transmit_buffer(sport); in imx_uart_int()
999 imx_uart_writel(sport, USR1_DTRD, USR1); in imx_uart_int()
1001 imx_uart_mctrl_check(sport); in imx_uart_int()
1012 imx_uart_writel(sport, USR1_AWAKE, USR1); in imx_uart_int()
1017 sport->port.icount.overrun++; in imx_uart_int()
1018 imx_uart_writel(sport, USR2_ORE, USR2); in imx_uart_int()
1022 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_int()
1032 struct imx_port *sport = (struct imx_port *)port; in imx_uart_tx_empty() local
1035 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; in imx_uart_tx_empty()
1038 if (sport->dma_is_txing) in imx_uart_tx_empty()
1047 struct imx_port *sport = (struct imx_port *)port; in imx_uart_get_mctrl() local
1048 unsigned int ret = imx_uart_get_hwmctrl(sport); in imx_uart_get_mctrl()
1050 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1058 struct imx_port *sport = (struct imx_port *)port; in imx_uart_set_mctrl() local
1068 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_set_mctrl()
1080 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_set_mctrl()
1083 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR; in imx_uart_set_mctrl()
1086 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_set_mctrl()
1088 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP; in imx_uart_set_mctrl()
1091 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport)); in imx_uart_set_mctrl()
1093 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1101 struct imx_port *sport = (struct imx_port *)port; in imx_uart_break_ctl() local
1105 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_break_ctl()
1107 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; in imx_uart_break_ctl()
1112 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_break_ctl()
1114 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_break_ctl()
1123 struct imx_port *sport = from_timer(sport, t, timer); in imx_uart_timeout() local
1126 if (sport->port.state) { in imx_uart_timeout()
1127 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_timeout()
1128 imx_uart_mctrl_check(sport); in imx_uart_timeout()
1129 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_timeout()
1131 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1145 struct imx_port *sport = data; in imx_uart_dma_rx_callback() local
1146 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1147 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1148 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1150 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1156 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1159 imx_uart_clear_rx_errors(sport); in imx_uart_dma_rx_callback()
1163 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1180 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1190 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1194 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1197 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1201 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1203 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1212 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1220 static int imx_uart_start_rx_dma(struct imx_port *sport) in imx_uart_start_rx_dma() argument
1222 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1223 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1224 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1228 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1229 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1230 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_start_rx_dma()
1232 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); in imx_uart_start_rx_dma()
1240 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1249 desc->callback_param = sport; in imx_uart_start_rx_dma()
1252 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1253 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1258 static void imx_uart_clear_rx_errors(struct imx_port *sport) in imx_uart_clear_rx_errors() argument
1260 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1263 usr1 = imx_uart_readl(sport, USR1); in imx_uart_clear_rx_errors()
1264 usr2 = imx_uart_readl(sport, USR2); in imx_uart_clear_rx_errors()
1267 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1268 imx_uart_writel(sport, USR2_BRCD, USR2); in imx_uart_clear_rx_errors()
1269 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1271 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1275 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1276 imx_uart_writel(sport, USR1_FRAMERR, USR1); in imx_uart_clear_rx_errors()
1278 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1279 imx_uart_writel(sport, USR1_PARITYERR, USR1); in imx_uart_clear_rx_errors()
1284 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1285 imx_uart_writel(sport, USR2_ORE, USR2); in imx_uart_clear_rx_errors()
1295 static void imx_uart_setup_ufcr(struct imx_port *sport, in imx_uart_setup_ufcr() argument
1301 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); in imx_uart_setup_ufcr()
1303 imx_uart_writel(sport, val, UFCR); in imx_uart_setup_ufcr()
1306 static void imx_uart_dma_exit(struct imx_port *sport) in imx_uart_dma_exit() argument
1308 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1309 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1310 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1311 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1312 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1313 kfree(sport->rx_buf); in imx_uart_dma_exit()
1314 sport->rx_buf = NULL; in imx_uart_dma_exit()
1317 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1318 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1319 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1320 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1324 static int imx_uart_dma_init(struct imx_port *sport) in imx_uart_dma_init() argument
1327 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1331 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); in imx_uart_dma_init()
1332 if (!sport->dma_chan_rx) { in imx_uart_dma_init()
1339 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1343 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1349 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); in imx_uart_dma_init()
1350 if (!sport->rx_buf) { in imx_uart_dma_init()
1354 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1357 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); in imx_uart_dma_init()
1358 if (!sport->dma_chan_tx) { in imx_uart_dma_init()
1365 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1368 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1376 imx_uart_dma_exit(sport); in imx_uart_dma_init()
1380 static void imx_uart_enable_dma(struct imx_port *sport) in imx_uart_enable_dma() argument
1384 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA); in imx_uart_enable_dma()
1387 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_enable_dma()
1389 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_enable_dma()
1391 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1394 static void imx_uart_disable_dma(struct imx_port *sport) in imx_uart_disable_dma() argument
1399 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_disable_dma()
1401 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_disable_dma()
1403 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_disable_dma()
1405 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1413 struct imx_port *sport = (struct imx_port *)port; in imx_uart_startup() local
1419 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1422 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1424 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1428 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_startup()
1433 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_startup()
1439 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); in imx_uart_startup()
1442 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) in imx_uart_startup()
1445 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_startup()
1449 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_startup()
1451 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_startup()
1453 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_startup()
1459 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1); in imx_uart_startup()
1460 imx_uart_writel(sport, USR2_ORE, USR2); in imx_uart_startup()
1462 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; in imx_uart_startup()
1464 if (sport->have_rtscts) in imx_uart_startup()
1467 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_startup()
1469 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR); in imx_uart_startup()
1470 if (!sport->dma_is_enabled) in imx_uart_startup()
1472 if (sport->inverted_rx) in imx_uart_startup()
1474 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_startup()
1476 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT; in imx_uart_startup()
1480 if (sport->inverted_tx) in imx_uart_startup()
1483 if (!imx_uart_is_imx1(sport)) { in imx_uart_startup()
1486 if (sport->dte_mode) in imx_uart_startup()
1490 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_startup()
1492 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN; in imx_uart_startup()
1494 if (!sport->have_rtscts) in imx_uart_startup()
1500 if (!imx_uart_is_imx1(sport)) in imx_uart_startup()
1502 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_startup()
1507 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1510 imx_uart_enable_dma(sport); in imx_uart_startup()
1511 imx_uart_start_rx_dma(sport); in imx_uart_startup()
1513 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_startup()
1515 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_startup()
1517 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_startup()
1519 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_startup()
1522 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_startup()
1529 struct imx_port *sport = (struct imx_port *)port; in imx_uart_shutdown() local
1533 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1534 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1535 if (sport->dma_is_txing) { in imx_uart_shutdown()
1536 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1537 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1538 sport->dma_is_txing = 0; in imx_uart_shutdown()
1540 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1541 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1542 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1544 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1547 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1550 imx_uart_disable_dma(sport); in imx_uart_shutdown()
1551 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1552 imx_uart_dma_exit(sport); in imx_uart_shutdown()
1555 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1557 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1558 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_shutdown()
1560 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_shutdown()
1561 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1566 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1572 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1574 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_shutdown()
1576 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_shutdown()
1578 ucr4 = imx_uart_readl(sport, UCR4); in imx_uart_shutdown()
1580 imx_uart_writel(sport, ucr4, UCR4); in imx_uart_shutdown()
1582 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1584 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1585 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1591 struct imx_port *sport = (struct imx_port *)port; in imx_uart_flush_buffer() local
1592 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1596 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1599 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1600 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1601 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1604 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1606 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_flush_buffer()
1608 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_flush_buffer()
1609 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1623 ubir = imx_uart_readl(sport, UBIR); in imx_uart_flush_buffer()
1624 ubmr = imx_uart_readl(sport, UBMR); in imx_uart_flush_buffer()
1625 uts = imx_uart_readl(sport, IMX21_UTS); in imx_uart_flush_buffer()
1627 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_flush_buffer()
1629 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_flush_buffer()
1631 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_flush_buffer()
1635 imx_uart_writel(sport, ubir, UBIR); in imx_uart_flush_buffer()
1636 imx_uart_writel(sport, ubmr, UBMR); in imx_uart_flush_buffer()
1637 imx_uart_writel(sport, uts, IMX21_UTS); in imx_uart_flush_buffer()
1644 struct imx_port *sport = (struct imx_port *)port; in imx_uart_set_termios() local
1663 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1671 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_set_termios()
1677 old_ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_set_termios()
1684 if (!sport->have_rtscts) in imx_uart_set_termios()
1694 imx_uart_rts_active(sport, &ucr2); in imx_uart_set_termios()
1696 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_set_termios()
1717 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1719 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1721 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1726 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1728 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1730 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1736 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1740 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1748 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1750 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1752 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1758 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1761 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1770 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_set_termios()
1772 imx_uart_writel(sport, ufcr, UFCR); in imx_uart_set_termios()
1783 old_ubir = imx_uart_readl(sport, UBIR); in imx_uart_set_termios()
1784 old_ubmr = imx_uart_readl(sport, UBMR); in imx_uart_set_termios()
1786 imx_uart_writel(sport, num, UBIR); in imx_uart_set_termios()
1787 imx_uart_writel(sport, denom, UBMR); in imx_uart_set_termios()
1790 if (!imx_uart_is_imx1(sport)) in imx_uart_set_termios()
1791 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1794 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_set_termios()
1796 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1797 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1799 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_set_termios()
1804 struct imx_port *sport = (struct imx_port *)port; in imx_uart_type() local
1806 return sport->port.type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1814 struct imx_port *sport = (struct imx_port *)port; in imx_uart_config_port() local
1817 sport->port.type = PORT_IMX; in imx_uart_config_port()
1828 struct imx_port *sport = (struct imx_port *)port; in imx_uart_verify_port() local
1833 if (sport->port.irq != ser->irq) in imx_uart_verify_port()
1837 if (sport->port.uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1839 if (sport->port.mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1841 if (sport->port.iobase != ser->port) in imx_uart_verify_port()
1852 struct imx_port *sport = (struct imx_port *)port; in imx_uart_poll_init() local
1857 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1860 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1862 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1864 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_poll_init()
1866 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_poll_init()
1875 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_poll_init()
1876 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_poll_init()
1878 if (imx_uart_is_imx1(sport)) in imx_uart_poll_init()
1887 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_poll_init()
1888 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_poll_init()
1891 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); in imx_uart_poll_init()
1892 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); in imx_uart_poll_init()
1894 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_poll_init()
1901 struct imx_port *sport = (struct imx_port *)port; in imx_uart_poll_get_char() local
1902 if (!(imx_uart_readl(sport, USR2) & USR2_RDR)) in imx_uart_poll_get_char()
1905 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA; in imx_uart_poll_get_char()
1910 struct imx_port *sport = (struct imx_port *)port; in imx_uart_poll_put_char() local
1915 status = imx_uart_readl(sport, USR1); in imx_uart_poll_put_char()
1919 imx_uart_writel(sport, c, URTX0); in imx_uart_poll_put_char()
1923 status = imx_uart_readl(sport, USR2); in imx_uart_poll_put_char()
1932 struct imx_port *sport = (struct imx_port *)port; in imx_uart_rs485_config() local
1936 if (!sport->have_rtscts && !sport->have_rtsgpio) in imx_uart_rs485_config()
1941 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1946 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_rs485_config()
1948 imx_uart_rts_active(sport, &ucr2); in imx_uart_rs485_config()
1950 imx_uart_rts_inactive(sport, &ucr2); in imx_uart_rs485_config()
1951 imx_uart_writel(sport, ucr2, UCR2); in imx_uart_rs485_config()
1992 struct imx_port *sport = (struct imx_port *)port; in imx_uart_console_putchar() local
1994 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL) in imx_uart_console_putchar()
1997 imx_uart_writel(sport, ch, URTX0); in imx_uart_console_putchar()
2006 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write() local
2012 if (sport->port.sysrq) in imx_uart_console_write()
2015 locked = spin_trylock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2017 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2022 imx_uart_ucrs_save(sport, &old_ucr); in imx_uart_console_write()
2025 if (imx_uart_is_imx1(sport)) in imx_uart_console_write()
2030 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_console_write()
2032 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2); in imx_uart_console_write()
2034 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2040 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC)); in imx_uart_console_write()
2042 imx_uart_ucrs_restore(sport, &old_ucr); in imx_uart_console_write()
2045 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_console_write()
2053 imx_uart_console_get_options(struct imx_port *sport, int *baud, in imx_uart_console_get_options() argument
2057 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) { in imx_uart_console_get_options()
2063 ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_console_get_options()
2078 ubir = imx_uart_readl(sport, UBIR) & 0xffff; in imx_uart_console_get_options()
2079 ubmr = imx_uart_readl(sport, UBMR) & 0xffff; in imx_uart_console_get_options()
2081 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7; in imx_uart_console_get_options()
2087 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2106 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2114 struct imx_port *sport; in imx_uart_console_setup() local
2128 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2129 if (sport == NULL) in imx_uart_console_setup()
2133 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2140 imx_uart_console_get_options(sport, &baud, &parity, &bits); in imx_uart_console_setup()
2142 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); in imx_uart_console_setup()
2144 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2147 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2151 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2153 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2191 static int imx_uart_probe_dt(struct imx_port *sport, in imx_uart_probe_dt() argument
2197 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe_dt()
2198 if (!sport->devdata) in imx_uart_probe_dt()
2207 sport->port.line = ret; in imx_uart_probe_dt()
2211 sport->have_rtscts = 1; in imx_uart_probe_dt()
2214 sport->dte_mode = 1; in imx_uart_probe_dt()
2217 sport->have_rtsgpio = 1; in imx_uart_probe_dt()
2220 sport->inverted_tx = 1; in imx_uart_probe_dt()
2223 sport->inverted_rx = 1; in imx_uart_probe_dt()
2228 static inline int imx_uart_probe_dt(struct imx_port *sport, in imx_uart_probe_dt() argument
2235 static void imx_uart_probe_pdata(struct imx_port *sport, in imx_uart_probe_pdata() argument
2240 sport->port.line = pdev->id; in imx_uart_probe_pdata()
2241 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; in imx_uart_probe_pdata()
2247 sport->have_rtscts = 1; in imx_uart_probe_pdata()
2252 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); in imx_trigger_start_tx() local
2255 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_start_tx()
2256 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2257 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2258 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_start_tx()
2265 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); in imx_trigger_stop_tx() local
2268 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_stop_tx()
2269 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2270 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2271 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_stop_tx()
2278 struct imx_port *sport; in imx_uart_probe() local
2285 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2286 if (!sport) in imx_uart_probe()
2289 ret = imx_uart_probe_dt(sport, pdev); in imx_uart_probe()
2291 imx_uart_probe_pdata(sport, pdev); in imx_uart_probe()
2295 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2297 sport->port.line); in imx_uart_probe()
2312 sport->port.dev = &pdev->dev; in imx_uart_probe()
2313 sport->port.mapbase = res->start; in imx_uart_probe()
2314 sport->port.membase = base; in imx_uart_probe()
2315 sport->port.type = PORT_IMX, in imx_uart_probe()
2316 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2317 sport->port.irq = rxirq; in imx_uart_probe()
2318 sport->port.fifosize = 32; in imx_uart_probe()
2319 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2320 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2321 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2322 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2323 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2325 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2326 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2327 return PTR_ERR(sport->gpios); in imx_uart_probe()
2329 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2330 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2331 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2336 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2337 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2338 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2343 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2346 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2353 sport->ucr1 = readl(sport->port.membase + UCR1); in imx_uart_probe()
2354 sport->ucr2 = readl(sport->port.membase + UCR2); in imx_uart_probe()
2355 sport->ucr3 = readl(sport->port.membase + UCR3); in imx_uart_probe()
2356 sport->ucr4 = readl(sport->port.membase + UCR4); in imx_uart_probe()
2357 sport->ufcr = readl(sport->port.membase + UFCR); in imx_uart_probe()
2359 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2361 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2365 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2366 (!sport->have_rtscts && !sport->have_rtsgpio)) in imx_uart_probe()
2374 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2375 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2376 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2377 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2381 imx_uart_rs485_config(&sport->port, &sport->port.rs485); in imx_uart_probe()
2384 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_probe()
2386 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_probe()
2388 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2395 u32 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_probe()
2397 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR); in imx_uart_probe()
2404 imx_uart_writel(sport, in imx_uart_probe()
2410 u32 ufcr = imx_uart_readl(sport, UFCR); in imx_uart_probe()
2412 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR); in imx_uart_probe()
2414 if (!imx_uart_is_imx1(sport)) in imx_uart_probe()
2416 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_probe()
2419 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2421 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2422 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2423 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2424 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2432 dev_name(&pdev->dev), sport); in imx_uart_probe()
2440 dev_name(&pdev->dev), sport); in imx_uart_probe()
2448 dev_name(&pdev->dev), sport); in imx_uart_probe()
2456 dev_name(&pdev->dev), sport); in imx_uart_probe()
2463 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2465 platform_set_drvdata(pdev, sport); in imx_uart_probe()
2467 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2472 struct imx_port *sport = platform_get_drvdata(pdev); in imx_uart_remove() local
2474 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2477 static void imx_uart_restore_context(struct imx_port *sport) in imx_uart_restore_context() argument
2481 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_restore_context()
2482 if (!sport->context_saved) { in imx_uart_restore_context()
2483 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2487 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2488 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2489 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2490 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2491 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2492 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2493 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2494 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2495 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2496 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2497 sport->context_saved = false; in imx_uart_restore_context()
2498 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2501 static void imx_uart_save_context(struct imx_port *sport) in imx_uart_save_context() argument
2506 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_save_context()
2507 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2508 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2509 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2510 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2511 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2512 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2513 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2514 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2515 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2516 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2517 sport->context_saved = true; in imx_uart_save_context()
2518 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_save_context()
2521 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on) in imx_uart_enable_wakeup() argument
2525 ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_enable_wakeup()
2527 imx_uart_writel(sport, USR1_AWAKE, USR1); in imx_uart_enable_wakeup()
2532 imx_uart_writel(sport, ucr3, UCR3); in imx_uart_enable_wakeup()
2534 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2535 u32 ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_enable_wakeup()
2540 imx_uart_writel(sport, ucr1, UCR1); in imx_uart_enable_wakeup()
2546 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_suspend_noirq() local
2548 imx_uart_save_context(sport); in imx_uart_suspend_noirq()
2550 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2559 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_resume_noirq() local
2564 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2568 imx_uart_restore_context(sport); in imx_uart_resume_noirq()
2575 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_suspend() local
2578 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2579 disable_irq(sport->port.irq); in imx_uart_suspend()
2581 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2586 imx_uart_enable_wakeup(sport, true); in imx_uart_suspend()
2593 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_resume() local
2596 imx_uart_enable_wakeup(sport, false); in imx_uart_resume()
2598 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2599 enable_irq(sport->port.irq); in imx_uart_resume()
2601 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2608 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_freeze() local
2610 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2612 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2617 struct imx_port *sport = dev_get_drvdata(dev); in imx_uart_thaw() local
2619 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2621 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()