Lines Matching +full:rx +full:- +full:float +full:- +full:inactive
1 // SPDX-License-Identifier: GPL-2.0+
30 #include <linux/dma-mapping.h>
33 #include <linux/platform_data/serial-imx.h>
34 #include <linux/platform_data/dma-imx.h>
125 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
154 #define UTS_LOOP (1<<12) /* Loop tx and rx */
161 /* We've been assigned a range on the "Low-density serial ports" major */
174 #define DRIVER_NAME "IMX-uart"
268 .name = "imx1-uart",
271 .name = "imx21-uart",
274 .name = "imx53-uart",
277 .name = "imx6q-uart",
286 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
287 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
288 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
289 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
298 sport->ucr1 = val; in imx_uart_writel()
301 sport->ucr2 = val; in imx_uart_writel()
304 sport->ucr3 = val; in imx_uart_writel()
307 sport->ucr4 = val; in imx_uart_writel()
310 sport->ufcr = val; in imx_uart_writel()
315 writel(val, sport->port.membase + offset); in imx_uart_writel()
322 return sport->ucr1; in imx_uart_readl()
331 if (!(sport->ucr2 & UCR2_SRST)) in imx_uart_readl()
332 sport->ucr2 = readl(sport->port.membase + offset); in imx_uart_readl()
333 return sport->ucr2; in imx_uart_readl()
336 return sport->ucr3; in imx_uart_readl()
339 return sport->ucr4; in imx_uart_readl()
342 return sport->ufcr; in imx_uart_readl()
345 return readl(sport->port.membase + offset); in imx_uart_readl()
351 return sport->devdata->uts_reg; in imx_uart_uts_reg()
356 return sport->devdata->devtype == IMX1_UART; in imx_uart_is_imx1()
361 return sport->devdata->devtype == IMX21_UART; in imx_uart_is_imx21()
366 return sport->devdata->devtype == IMX53_UART; in imx_uart_is_imx53()
371 return sport->devdata->devtype == IMX6Q_UART; in imx_uart_is_imx6q()
381 ucr->ucr1 = imx_uart_readl(sport, UCR1); in imx_uart_ucrs_save()
382 ucr->ucr2 = imx_uart_readl(sport, UCR2); in imx_uart_ucrs_save()
383 ucr->ucr3 = imx_uart_readl(sport, UCR3); in imx_uart_ucrs_save()
390 imx_uart_writel(sport, ucr->ucr1, UCR1); in imx_uart_ucrs_restore()
391 imx_uart_writel(sport, ucr->ucr2, UCR2); in imx_uart_ucrs_restore()
392 imx_uart_writel(sport, ucr->ucr3, UCR3); in imx_uart_ucrs_restore()
401 sport->port.mctrl |= TIOCM_RTS; in imx_uart_rts_active()
402 mctrl_gpio_set(sport->gpios, sport->port.mctrl); in imx_uart_rts_active()
411 sport->port.mctrl &= ~TIOCM_RTS; in imx_uart_rts_inactive()
412 mctrl_gpio_set(sport->gpios, sport->port.mctrl); in imx_uart_rts_inactive()
435 if (sport->dma_is_enabled) { in imx_uart_start_rx()
453 if (sport->tx_state == OFF) in imx_uart_stop_tx()
460 if (sport->dma_is_txing) in imx_uart_stop_tx()
477 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_stop_tx()
478 if (sport->tx_state == SEND) { in imx_uart_stop_tx()
479 sport->tx_state = WAIT_AFTER_SEND; in imx_uart_stop_tx()
480 start_hrtimer_ms(&sport->trigger_stop_tx, in imx_uart_stop_tx()
481 port->rs485.delay_rts_after_send); in imx_uart_stop_tx()
485 if (sport->tx_state == WAIT_AFTER_RTS || in imx_uart_stop_tx()
486 sport->tx_state == WAIT_AFTER_SEND) { in imx_uart_stop_tx()
489 hrtimer_try_to_cancel(&sport->trigger_start_tx); in imx_uart_stop_tx()
492 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_stop_tx()
500 sport->tx_state = OFF; in imx_uart_stop_tx()
503 sport->tx_state = OFF; in imx_uart_stop_tx()
516 if (sport->dma_is_enabled) { in imx_uart_stop_rx()
533 mod_timer(&sport->timer, jiffies); in imx_uart_enable_ms()
535 mctrl_gpio_enable_ms(sport->gpios); in imx_uart_enable_ms()
543 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_transmit_buffer()
545 if (sport->port.x_char) { in imx_uart_transmit_buffer()
547 imx_uart_writel(sport, sport->port.x_char, URTX0); in imx_uart_transmit_buffer()
548 sport->port.icount.tx++; in imx_uart_transmit_buffer()
549 sport->port.x_char = 0; in imx_uart_transmit_buffer()
553 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { in imx_uart_transmit_buffer()
554 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
558 if (sport->dma_is_enabled) { in imx_uart_transmit_buffer()
561 * We've just sent a X-char Ensure the TX DMA is enabled in imx_uart_transmit_buffer()
566 if (sport->dma_is_txing) { in imx_uart_transmit_buffer()
579 /* send xmit->buf[xmit->tail] in imx_uart_transmit_buffer()
581 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0); in imx_uart_transmit_buffer()
582 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in imx_uart_transmit_buffer()
583 sport->port.icount.tx++; in imx_uart_transmit_buffer()
587 uart_write_wakeup(&sport->port); in imx_uart_transmit_buffer()
590 imx_uart_stop_tx(&sport->port); in imx_uart_transmit_buffer()
596 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_dma_tx_callback()
597 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx_callback()
601 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
603 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx_callback()
610 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); in imx_uart_dma_tx_callback()
611 sport->port.icount.tx += sport->tx_bytes; in imx_uart_dma_tx_callback()
613 dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); in imx_uart_dma_tx_callback()
615 sport->dma_is_txing = 0; in imx_uart_dma_tx_callback()
618 uart_write_wakeup(&sport->port); in imx_uart_dma_tx_callback()
620 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) in imx_uart_dma_tx_callback()
622 else if (sport->port.rs485.flags & SER_RS485_ENABLED) { in imx_uart_dma_tx_callback()
628 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_dma_tx_callback()
634 struct circ_buf *xmit = &sport->port.state->xmit; in imx_uart_dma_tx()
635 struct scatterlist *sgl = sport->tx_sgl; in imx_uart_dma_tx()
637 struct dma_chan *chan = sport->dma_chan_tx; in imx_uart_dma_tx()
638 struct device *dev = sport->port.dev; in imx_uart_dma_tx()
642 if (sport->dma_is_txing) in imx_uart_dma_tx()
649 sport->tx_bytes = uart_circ_chars_pending(xmit); in imx_uart_dma_tx()
651 if (xmit->tail < xmit->head || xmit->head == 0) { in imx_uart_dma_tx()
652 sport->dma_tx_nents = 1; in imx_uart_dma_tx()
653 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); in imx_uart_dma_tx()
655 sport->dma_tx_nents = 2; in imx_uart_dma_tx()
657 sg_set_buf(sgl, xmit->buf + xmit->tail, in imx_uart_dma_tx()
658 UART_XMIT_SIZE - xmit->tail); in imx_uart_dma_tx()
659 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in imx_uart_dma_tx()
662 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_dma_tx()
670 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, in imx_uart_dma_tx()
675 desc->callback = imx_uart_dma_tx_callback; in imx_uart_dma_tx()
676 desc->callback_param = sport; in imx_uart_dma_tx()
686 sport->dma_is_txing = 1; in imx_uart_dma_tx()
698 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit)) in imx_uart_start_tx()
702 * We cannot simply do nothing here if sport->tx_state == SEND already in imx_uart_start_tx()
707 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_start_tx()
708 if (sport->tx_state == OFF) { in imx_uart_start_tx()
710 if (port->rs485.flags & SER_RS485_RTS_ON_SEND) in imx_uart_start_tx()
716 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in imx_uart_start_tx()
719 sport->tx_state = WAIT_AFTER_RTS; in imx_uart_start_tx()
720 start_hrtimer_ms(&sport->trigger_start_tx, in imx_uart_start_tx()
721 port->rs485.delay_rts_before_send); in imx_uart_start_tx()
725 if (sport->tx_state == WAIT_AFTER_SEND in imx_uart_start_tx()
726 || sport->tx_state == WAIT_AFTER_RTS) { in imx_uart_start_tx()
728 hrtimer_try_to_cancel(&sport->trigger_stop_tx); in imx_uart_start_tx()
733 * tx-callback. in imx_uart_start_tx()
735 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
741 sport->tx_state = SEND; in imx_uart_start_tx()
744 sport->tx_state = SEND; in imx_uart_start_tx()
747 if (!sport->dma_is_enabled) { in imx_uart_start_tx()
752 if (sport->dma_is_enabled) { in imx_uart_start_tx()
753 if (sport->port.x_char) { in imx_uart_start_tx()
754 /* We have X-char to send, so enable TX IRQ and in imx_uart_start_tx()
755 * disable TX DMA to let TX interrupt to send X-char */ in imx_uart_start_tx()
763 if (!uart_circ_empty(&port->state->xmit) && in imx_uart_start_tx()
777 uart_handle_cts_change(&sport->port, !!usr1); in __imx_uart_rtsint()
778 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in __imx_uart_rtsint()
788 spin_lock(&sport->port.lock); in imx_uart_rtsint()
792 spin_unlock(&sport->port.lock); in imx_uart_rtsint()
801 spin_lock(&sport->port.lock); in imx_uart_txint()
803 spin_unlock(&sport->port.lock); in imx_uart_txint()
810 unsigned int rx, flg, ignored = 0; in __imx_uart_rxint() local
811 struct tty_port *port = &sport->port.state->port; in __imx_uart_rxint()
817 sport->port.icount.rx++; in __imx_uart_rxint()
819 rx = imx_uart_readl(sport, URXD0); in __imx_uart_rxint()
824 if (uart_handle_break(&sport->port)) in __imx_uart_rxint()
828 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in __imx_uart_rxint()
831 if (unlikely(rx & URXD_ERR)) { in __imx_uart_rxint()
832 if (rx & URXD_BRK) in __imx_uart_rxint()
833 sport->port.icount.brk++; in __imx_uart_rxint()
834 else if (rx & URXD_PRERR) in __imx_uart_rxint()
835 sport->port.icount.parity++; in __imx_uart_rxint()
836 else if (rx & URXD_FRMERR) in __imx_uart_rxint()
837 sport->port.icount.frame++; in __imx_uart_rxint()
838 if (rx & URXD_OVRRUN) in __imx_uart_rxint()
839 sport->port.icount.overrun++; in __imx_uart_rxint()
841 if (rx & sport->port.ignore_status_mask) { in __imx_uart_rxint()
847 rx &= (sport->port.read_status_mask | 0xFF); in __imx_uart_rxint()
849 if (rx & URXD_BRK) in __imx_uart_rxint()
851 else if (rx & URXD_PRERR) in __imx_uart_rxint()
853 else if (rx & URXD_FRMERR) in __imx_uart_rxint()
855 if (rx & URXD_OVRRUN) in __imx_uart_rxint()
858 sport->port.sysrq = 0; in __imx_uart_rxint()
861 if (sport->port.ignore_status_mask & URXD_DUMMY_READ) in __imx_uart_rxint()
864 if (tty_insert_flip_char(port, rx, flg) == 0) in __imx_uart_rxint()
865 sport->port.icount.buf_overrun++; in __imx_uart_rxint()
879 spin_lock(&sport->port.lock); in imx_uart_rxint()
883 spin_unlock(&sport->port.lock); in imx_uart_rxint()
906 if (sport->dte_mode) in imx_uart_get_hwmctrl()
921 changed = status ^ sport->old_status; in imx_uart_mctrl_check()
926 sport->old_status = status; in imx_uart_mctrl_check()
929 sport->port.icount.rng++; in imx_uart_mctrl_check()
931 sport->port.icount.dsr++; in imx_uart_mctrl_check()
933 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); in imx_uart_mctrl_check()
935 uart_handle_cts_change(&sport->port, status & TIOCM_CTS); in imx_uart_mctrl_check()
937 wake_up_interruptible(&sport->port.state->port.delta_msr_wait); in imx_uart_mctrl_check()
952 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_int()
964 * actions, for example if a character that sits in the RX FIFO and that in imx_uart_int()
1017 sport->port.icount.overrun++; in imx_uart_int()
1022 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_int()
1038 if (sport->dma_is_txing) in imx_uart_tx_empty()
1050 mctrl_gpio_get(sport->gpios, &ret); in imx_uart_get_mctrl()
1061 if (!(port->rs485.flags & SER_RS485_ENABLED)) { in imx_uart_set_mctrl()
1093 mctrl_gpio_set(sport->gpios, mctrl); in imx_uart_set_mctrl()
1105 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_break_ctl()
1114 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_break_ctl()
1118 * This is our per-port timeout handler, for checking the
1126 if (sport->port.state) { in imx_uart_timeout()
1127 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_timeout()
1129 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_timeout()
1131 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); in imx_uart_timeout()
1136 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1137 * [1] the RX DMA buffer is full.
1146 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_dma_rx_callback()
1147 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_dma_rx_callback()
1148 struct tty_port *port = &sport->port.state->port; in imx_uart_dma_rx_callback()
1150 struct circ_buf *rx_ring = &sport->rx_ring; in imx_uart_dma_rx_callback()
1156 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); in imx_uart_dma_rx_callback()
1163 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { in imx_uart_dma_rx_callback()
1166 * The state-residue variable represents the empty space in imx_uart_dma_rx_callback()
1169 * length - DMA transaction residue. The UART script from the in imx_uart_dma_rx_callback()
1171 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4). in imx_uart_dma_rx_callback()
1177 rx_ring->head = sg_dma_len(sgl) - state.residue; in imx_uart_dma_rx_callback()
1180 bd_size = sg_dma_len(sgl) / sport->rx_periods; in imx_uart_dma_rx_callback()
1181 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size; in imx_uart_dma_rx_callback()
1183 if (rx_ring->head <= sg_dma_len(sgl) && in imx_uart_dma_rx_callback()
1184 rx_ring->head > rx_ring->tail) { in imx_uart_dma_rx_callback()
1187 r_bytes = rx_ring->head - rx_ring->tail; in imx_uart_dma_rx_callback()
1189 /* CPU claims ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1190 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1194 sport->rx_buf + rx_ring->tail, r_bytes); in imx_uart_dma_rx_callback()
1196 /* UART retrieves ownership of RX DMA buffer */ in imx_uart_dma_rx_callback()
1197 dma_sync_sg_for_device(sport->port.dev, sgl, 1, in imx_uart_dma_rx_callback()
1201 sport->port.icount.buf_overrun++; in imx_uart_dma_rx_callback()
1203 sport->port.icount.rx += w_bytes; in imx_uart_dma_rx_callback()
1205 WARN_ON(rx_ring->head > sg_dma_len(sgl)); in imx_uart_dma_rx_callback()
1206 WARN_ON(rx_ring->head <= rx_ring->tail); in imx_uart_dma_rx_callback()
1212 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes); in imx_uart_dma_rx_callback()
1216 /* RX DMA buffer periods */
1222 struct scatterlist *sgl = &sport->rx_sgl; in imx_uart_start_rx_dma()
1223 struct dma_chan *chan = sport->dma_chan_rx; in imx_uart_start_rx_dma()
1224 struct device *dev = sport->port.dev; in imx_uart_start_rx_dma()
1228 sport->rx_ring.head = 0; in imx_uart_start_rx_dma()
1229 sport->rx_ring.tail = 0; in imx_uart_start_rx_dma()
1230 sport->rx_periods = RX_DMA_PERIODS; in imx_uart_start_rx_dma()
1232 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); in imx_uart_start_rx_dma()
1235 dev_err(dev, "DMA mapping error for RX.\n"); in imx_uart_start_rx_dma()
1236 return -EINVAL; in imx_uart_start_rx_dma()
1240 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods, in imx_uart_start_rx_dma()
1245 dev_err(dev, "We cannot prepare for the RX slave dma!\n"); in imx_uart_start_rx_dma()
1246 return -EINVAL; in imx_uart_start_rx_dma()
1248 desc->callback = imx_uart_dma_rx_callback; in imx_uart_start_rx_dma()
1249 desc->callback_param = sport; in imx_uart_start_rx_dma()
1251 dev_dbg(dev, "RX: prepare for the DMA.\n"); in imx_uart_start_rx_dma()
1252 sport->dma_is_rxing = 1; in imx_uart_start_rx_dma()
1253 sport->rx_cookie = dmaengine_submit(desc); in imx_uart_start_rx_dma()
1260 struct tty_port *port = &sport->port.state->port; in imx_uart_clear_rx_errors()
1267 sport->port.icount.brk++; in imx_uart_clear_rx_errors()
1269 uart_handle_break(&sport->port); in imx_uart_clear_rx_errors()
1271 sport->port.icount.buf_overrun++; in imx_uart_clear_rx_errors()
1275 sport->port.icount.frame++; in imx_uart_clear_rx_errors()
1278 sport->port.icount.parity++; in imx_uart_clear_rx_errors()
1284 sport->port.icount.overrun++; in imx_uart_clear_rx_errors()
1308 if (sport->dma_chan_rx) { in imx_uart_dma_exit()
1309 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_dma_exit()
1310 dma_release_channel(sport->dma_chan_rx); in imx_uart_dma_exit()
1311 sport->dma_chan_rx = NULL; in imx_uart_dma_exit()
1312 sport->rx_cookie = -EINVAL; in imx_uart_dma_exit()
1313 kfree(sport->rx_buf); in imx_uart_dma_exit()
1314 sport->rx_buf = NULL; in imx_uart_dma_exit()
1317 if (sport->dma_chan_tx) { in imx_uart_dma_exit()
1318 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_dma_exit()
1319 dma_release_channel(sport->dma_chan_tx); in imx_uart_dma_exit()
1320 sport->dma_chan_tx = NULL; in imx_uart_dma_exit()
1327 struct device *dev = sport->port.dev; in imx_uart_dma_init()
1330 /* Prepare for RX : */ in imx_uart_dma_init()
1331 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); in imx_uart_dma_init()
1332 if (!sport->dma_chan_rx) { in imx_uart_dma_init()
1334 ret = -EINVAL; in imx_uart_dma_init()
1339 slave_config.src_addr = sport->port.mapbase + URXD0; in imx_uart_dma_init()
1342 slave_config.src_maxburst = RXTL_DMA - 1; in imx_uart_dma_init()
1343 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); in imx_uart_dma_init()
1345 dev_err(dev, "error in RX dma configuration.\n"); in imx_uart_dma_init()
1349 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL); in imx_uart_dma_init()
1350 if (!sport->rx_buf) { in imx_uart_dma_init()
1351 ret = -ENOMEM; in imx_uart_dma_init()
1354 sport->rx_ring.buf = sport->rx_buf; in imx_uart_dma_init()
1357 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); in imx_uart_dma_init()
1358 if (!sport->dma_chan_tx) { in imx_uart_dma_init()
1360 ret = -EINVAL; in imx_uart_dma_init()
1365 slave_config.dst_addr = sport->port.mapbase + URTX0; in imx_uart_dma_init()
1368 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); in imx_uart_dma_init()
1391 sport->dma_is_enabled = 1; in imx_uart_enable_dma()
1405 sport->dma_is_enabled = 0; in imx_uart_disable_dma()
1408 /* half the RX buffer size */
1419 retval = clk_prepare_enable(sport->clk_per); in imx_uart_startup()
1422 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_startup()
1424 clk_disable_unprepare(sport->clk_per); in imx_uart_startup()
1445 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_startup()
1453 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_startup()
1464 if (sport->have_rtscts) in imx_uart_startup()
1470 if (!sport->dma_is_enabled) in imx_uart_startup()
1472 if (sport->inverted_rx) in imx_uart_startup()
1480 if (sport->inverted_tx) in imx_uart_startup()
1486 if (sport->dte_mode) in imx_uart_startup()
1494 if (!sport->have_rtscts) in imx_uart_startup()
1497 * make sure the edge sensitive RTS-irq is disabled, in imx_uart_startup()
1507 imx_uart_enable_ms(&sport->port); in imx_uart_startup()
1522 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_startup()
1533 if (sport->dma_is_enabled) { in imx_uart_shutdown()
1534 dmaengine_terminate_sync(sport->dma_chan_tx); in imx_uart_shutdown()
1535 if (sport->dma_is_txing) { in imx_uart_shutdown()
1536 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], in imx_uart_shutdown()
1537 sport->dma_tx_nents, DMA_TO_DEVICE); in imx_uart_shutdown()
1538 sport->dma_is_txing = 0; in imx_uart_shutdown()
1540 dmaengine_terminate_sync(sport->dma_chan_rx); in imx_uart_shutdown()
1541 if (sport->dma_is_rxing) { in imx_uart_shutdown()
1542 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, in imx_uart_shutdown()
1544 sport->dma_is_rxing = 0; in imx_uart_shutdown()
1547 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1551 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1555 mctrl_gpio_disable_ms(sport->gpios); in imx_uart_shutdown()
1557 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1561 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1566 del_timer_sync(&sport->timer); in imx_uart_shutdown()
1572 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_shutdown()
1582 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_shutdown()
1584 clk_disable_unprepare(sport->clk_per); in imx_uart_shutdown()
1585 clk_disable_unprepare(sport->clk_ipg); in imx_uart_shutdown()
1592 struct scatterlist *sgl = &sport->tx_sgl[0]; in imx_uart_flush_buffer()
1596 if (!sport->dma_chan_tx) in imx_uart_flush_buffer()
1599 sport->tx_bytes = 0; in imx_uart_flush_buffer()
1600 dmaengine_terminate_all(sport->dma_chan_tx); in imx_uart_flush_buffer()
1601 if (sport->dma_is_txing) { in imx_uart_flush_buffer()
1604 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, in imx_uart_flush_buffer()
1609 sport->dma_is_txing = 0; in imx_uart_flush_buffer()
1617 * and UTS[6-3]". in imx_uart_flush_buffer()
1631 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0)) in imx_uart_flush_buffer()
1648 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in imx_uart_set_termios()
1656 while ((termios->c_cflag & CSIZE) != CS7 && in imx_uart_set_termios()
1657 (termios->c_cflag & CSIZE) != CS8) { in imx_uart_set_termios()
1658 termios->c_cflag &= ~CSIZE; in imx_uart_set_termios()
1659 termios->c_cflag |= old_csize; in imx_uart_set_termios()
1663 del_timer_sync(&sport->timer); in imx_uart_set_termios()
1668 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in imx_uart_set_termios()
1671 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_set_termios()
1681 if ((termios->c_cflag & CSIZE) == CS8) in imx_uart_set_termios()
1684 if (!sport->have_rtscts) in imx_uart_set_termios()
1685 termios->c_cflag &= ~CRTSCTS; in imx_uart_set_termios()
1687 if (port->rs485.flags & SER_RS485_ENABLED) { in imx_uart_set_termios()
1693 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_set_termios()
1698 } else if (termios->c_cflag & CRTSCTS) { in imx_uart_set_termios()
1701 * to have RTS inactive (which then should take precedence). in imx_uart_set_termios()
1707 if (termios->c_cflag & CRTSCTS) in imx_uart_set_termios()
1709 if (termios->c_cflag & CSTOPB) in imx_uart_set_termios()
1711 if (termios->c_cflag & PARENB) { in imx_uart_set_termios()
1713 if (termios->c_cflag & PARODD) in imx_uart_set_termios()
1717 sport->port.read_status_mask = 0; in imx_uart_set_termios()
1718 if (termios->c_iflag & INPCK) in imx_uart_set_termios()
1719 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); in imx_uart_set_termios()
1720 if (termios->c_iflag & (BRKINT | PARMRK)) in imx_uart_set_termios()
1721 sport->port.read_status_mask |= URXD_BRK; in imx_uart_set_termios()
1726 sport->port.ignore_status_mask = 0; in imx_uart_set_termios()
1727 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1728 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; in imx_uart_set_termios()
1729 if (termios->c_iflag & IGNBRK) { in imx_uart_set_termios()
1730 sport->port.ignore_status_mask |= URXD_BRK; in imx_uart_set_termios()
1735 if (termios->c_iflag & IGNPAR) in imx_uart_set_termios()
1736 sport->port.ignore_status_mask |= URXD_OVRRUN; in imx_uart_set_termios()
1739 if ((termios->c_cflag & CREAD) == 0) in imx_uart_set_termios()
1740 sport->port.ignore_status_mask |= URXD_DUMMY_READ; in imx_uart_set_termios()
1743 * Update the per-port timeout. in imx_uart_set_termios()
1745 uart_update_timeout(port, termios->c_cflag, baud); in imx_uart_set_termios()
1747 /* custom-baudrate handling */ in imx_uart_set_termios()
1748 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1750 baud = sport->port.uartclk / (quot * 16); in imx_uart_set_termios()
1752 div = sport->port.uartclk / (baud * 16); in imx_uart_set_termios()
1758 rational_best_approximation(16 * div * baud, sport->port.uartclk, in imx_uart_set_termios()
1761 tdiv64 = sport->port.uartclk; in imx_uart_set_termios()
1767 num -= 1; in imx_uart_set_termios()
1768 denom -= 1; in imx_uart_set_termios()
1791 imx_uart_writel(sport, sport->port.uartclk / div / 1000, in imx_uart_set_termios()
1796 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) in imx_uart_set_termios()
1797 imx_uart_enable_ms(&sport->port); in imx_uart_set_termios()
1799 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_set_termios()
1806 return sport->port.type == PORT_IMX ? "IMX" : NULL; in imx_uart_type()
1817 sport->port.type = PORT_IMX; in imx_uart_config_port()
1831 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) in imx_uart_verify_port()
1832 ret = -EINVAL; in imx_uart_verify_port()
1833 if (sport->port.irq != ser->irq) in imx_uart_verify_port()
1834 ret = -EINVAL; in imx_uart_verify_port()
1835 if (ser->io_type != UPIO_MEM) in imx_uart_verify_port()
1836 ret = -EINVAL; in imx_uart_verify_port()
1837 if (sport->port.uartclk / 16 != ser->baud_base) in imx_uart_verify_port()
1838 ret = -EINVAL; in imx_uart_verify_port()
1839 if (sport->port.mapbase != (unsigned long)ser->iomem_base) in imx_uart_verify_port()
1840 ret = -EINVAL; in imx_uart_verify_port()
1841 if (sport->port.iobase != ser->port) in imx_uart_verify_port()
1842 ret = -EINVAL; in imx_uart_verify_port()
1843 if (ser->hub6 != 0) in imx_uart_verify_port()
1844 ret = -EINVAL; in imx_uart_verify_port()
1857 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_poll_init()
1860 retval = clk_prepare_enable(sport->clk_per); in imx_uart_poll_init()
1862 clk_disable_unprepare(sport->clk_ipg); in imx_uart_poll_init()
1866 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_poll_init()
1871 * This prevents that a character that already sits in the RX fifo is in imx_uart_poll_init()
1894 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_poll_init()
1936 if (!sport->have_rtscts && !sport->have_rtsgpio) in imx_uart_rs485_config()
1937 rs485conf->flags &= ~SER_RS485_ENABLED; in imx_uart_rs485_config()
1939 if (rs485conf->flags & SER_RS485_ENABLED) { in imx_uart_rs485_config()
1940 /* Enable receiver if low-active RTS signal is requested */ in imx_uart_rs485_config()
1941 if (sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_rs485_config()
1942 !(rs485conf->flags & SER_RS485_RTS_ON_SEND)) in imx_uart_rs485_config()
1943 rs485conf->flags |= SER_RS485_RX_DURING_TX; in imx_uart_rs485_config()
1947 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND) in imx_uart_rs485_config()
1954 /* Make sure Rx is enabled in case Tx is active with Rx disabled */ in imx_uart_rs485_config()
1955 if (!(rs485conf->flags & SER_RS485_ENABLED) || in imx_uart_rs485_config()
1956 rs485conf->flags & SER_RS485_RX_DURING_TX) in imx_uart_rs485_config()
1959 port->rs485 = *rs485conf; in imx_uart_rs485_config()
2006 struct imx_port *sport = imx_uart_ports[co->index]; in imx_uart_console_write()
2012 if (sport->port.sysrq) in imx_uart_console_write()
2015 locked = spin_trylock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2017 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_console_write()
2034 uart_console_write(&sport->port, s, count, imx_uart_console_putchar); in imx_uart_console_write()
2045 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_console_write()
2085 ucfr_rfdiv = 6 - ucfr_rfdiv; in imx_uart_console_get_options()
2087 uartclk = clk_get_rate(sport->clk_per); in imx_uart_console_get_options()
2093 * without need of float support or long long division, in imx_uart_console_get_options()
2106 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n", in imx_uart_console_get_options()
2126 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports)) in imx_uart_console_setup()
2127 co->index = 0; in imx_uart_console_setup()
2128 sport = imx_uart_ports[co->index]; in imx_uart_console_setup()
2130 return -ENODEV; in imx_uart_console_setup()
2133 retval = clk_prepare_enable(sport->clk_ipg); in imx_uart_console_setup()
2144 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); in imx_uart_console_setup()
2147 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2151 retval = clk_prepare_enable(sport->clk_per); in imx_uart_console_setup()
2153 clk_disable_unprepare(sport->clk_ipg); in imx_uart_console_setup()
2166 .index = -1,
2194 struct device_node *np = pdev->dev.of_node; in imx_uart_probe_dt()
2197 sport->devdata = of_device_get_match_data(&pdev->dev); in imx_uart_probe_dt()
2198 if (!sport->devdata) in imx_uart_probe_dt()
2204 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); in imx_uart_probe_dt()
2207 sport->port.line = ret; in imx_uart_probe_dt()
2209 if (of_get_property(np, "uart-has-rtscts", NULL) || in imx_uart_probe_dt()
2210 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) in imx_uart_probe_dt()
2211 sport->have_rtscts = 1; in imx_uart_probe_dt()
2213 if (of_get_property(np, "fsl,dte-mode", NULL)) in imx_uart_probe_dt()
2214 sport->dte_mode = 1; in imx_uart_probe_dt()
2216 if (of_get_property(np, "rts-gpios", NULL)) in imx_uart_probe_dt()
2217 sport->have_rtsgpio = 1; in imx_uart_probe_dt()
2219 if (of_get_property(np, "fsl,inverted-tx", NULL)) in imx_uart_probe_dt()
2220 sport->inverted_tx = 1; in imx_uart_probe_dt()
2222 if (of_get_property(np, "fsl,inverted-rx", NULL)) in imx_uart_probe_dt()
2223 sport->inverted_rx = 1; in imx_uart_probe_dt()
2238 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); in imx_uart_probe_pdata()
2240 sport->port.line = pdev->id; in imx_uart_probe_pdata()
2241 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; in imx_uart_probe_pdata()
2246 if (pdata->flags & IMXUART_HAVE_RTSCTS) in imx_uart_probe_pdata()
2247 sport->have_rtscts = 1; in imx_uart_probe_pdata()
2255 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_start_tx()
2256 if (sport->tx_state == WAIT_AFTER_RTS) in imx_trigger_start_tx()
2257 imx_uart_start_tx(&sport->port); in imx_trigger_start_tx()
2258 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_start_tx()
2268 spin_lock_irqsave(&sport->port.lock, flags); in imx_trigger_stop_tx()
2269 if (sport->tx_state == WAIT_AFTER_SEND) in imx_trigger_stop_tx()
2270 imx_uart_stop_tx(&sport->port); in imx_trigger_stop_tx()
2271 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_trigger_stop_tx()
2285 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in imx_uart_probe()
2287 return -ENOMEM; in imx_uart_probe()
2295 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) { in imx_uart_probe()
2296 dev_err(&pdev->dev, "serial%d out of range\n", in imx_uart_probe()
2297 sport->port.line); in imx_uart_probe()
2298 return -EINVAL; in imx_uart_probe()
2302 base = devm_ioremap_resource(&pdev->dev, res); in imx_uart_probe()
2312 sport->port.dev = &pdev->dev; in imx_uart_probe()
2313 sport->port.mapbase = res->start; in imx_uart_probe()
2314 sport->port.membase = base; in imx_uart_probe()
2315 sport->port.type = PORT_IMX, in imx_uart_probe()
2316 sport->port.iotype = UPIO_MEM; in imx_uart_probe()
2317 sport->port.irq = rxirq; in imx_uart_probe()
2318 sport->port.fifosize = 32; in imx_uart_probe()
2319 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE); in imx_uart_probe()
2320 sport->port.ops = &imx_uart_pops; in imx_uart_probe()
2321 sport->port.rs485_config = imx_uart_rs485_config; in imx_uart_probe()
2322 sport->port.flags = UPF_BOOT_AUTOCONF; in imx_uart_probe()
2323 timer_setup(&sport->timer, imx_uart_timeout, 0); in imx_uart_probe()
2325 sport->gpios = mctrl_gpio_init(&sport->port, 0); in imx_uart_probe()
2326 if (IS_ERR(sport->gpios)) in imx_uart_probe()
2327 return PTR_ERR(sport->gpios); in imx_uart_probe()
2329 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in imx_uart_probe()
2330 if (IS_ERR(sport->clk_ipg)) { in imx_uart_probe()
2331 ret = PTR_ERR(sport->clk_ipg); in imx_uart_probe()
2332 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); in imx_uart_probe()
2336 sport->clk_per = devm_clk_get(&pdev->dev, "per"); in imx_uart_probe()
2337 if (IS_ERR(sport->clk_per)) { in imx_uart_probe()
2338 ret = PTR_ERR(sport->clk_per); in imx_uart_probe()
2339 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); in imx_uart_probe()
2343 sport->port.uartclk = clk_get_rate(sport->clk_per); in imx_uart_probe()
2346 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_probe()
2348 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret); in imx_uart_probe()
2353 sport->ucr1 = readl(sport->port.membase + UCR1); in imx_uart_probe()
2354 sport->ucr2 = readl(sport->port.membase + UCR2); in imx_uart_probe()
2355 sport->ucr3 = readl(sport->port.membase + UCR3); in imx_uart_probe()
2356 sport->ucr4 = readl(sport->port.membase + UCR4); in imx_uart_probe()
2357 sport->ufcr = readl(sport->port.membase + UFCR); in imx_uart_probe()
2359 ret = uart_get_rs485_mode(&sport->port); in imx_uart_probe()
2361 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2365 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2366 (!sport->have_rtscts && !sport->have_rtsgpio)) in imx_uart_probe()
2367 dev_err(&pdev->dev, "no RTS control, disabling rs485\n"); in imx_uart_probe()
2374 if (sport->port.rs485.flags & SER_RS485_ENABLED && in imx_uart_probe()
2375 sport->have_rtscts && !sport->have_rtsgpio && in imx_uart_probe()
2376 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) && in imx_uart_probe()
2377 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX))) in imx_uart_probe()
2378 dev_err(&pdev->dev, in imx_uart_probe()
2379 "low-active RTS not possible when receiver is off, enabling receiver\n"); in imx_uart_probe()
2381 imx_uart_rs485_config(&sport->port, &sport->port.rs485); in imx_uart_probe()
2388 if (!imx_uart_is_imx1(sport) && sport->dte_mode) { in imx_uart_probe()
2419 clk_disable_unprepare(sport->clk_ipg); in imx_uart_probe()
2421 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2422 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in imx_uart_probe()
2423 sport->trigger_start_tx.function = imx_trigger_start_tx; in imx_uart_probe()
2424 sport->trigger_stop_tx.function = imx_trigger_stop_tx; in imx_uart_probe()
2431 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0, in imx_uart_probe()
2432 dev_name(&pdev->dev), sport); in imx_uart_probe()
2434 dev_err(&pdev->dev, "failed to request rx irq: %d\n", in imx_uart_probe()
2439 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0, in imx_uart_probe()
2440 dev_name(&pdev->dev), sport); in imx_uart_probe()
2442 dev_err(&pdev->dev, "failed to request tx irq: %d\n", in imx_uart_probe()
2447 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0, in imx_uart_probe()
2448 dev_name(&pdev->dev), sport); in imx_uart_probe()
2450 dev_err(&pdev->dev, "failed to request rts irq: %d\n", in imx_uart_probe()
2455 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0, in imx_uart_probe()
2456 dev_name(&pdev->dev), sport); in imx_uart_probe()
2458 dev_err(&pdev->dev, "failed to request irq: %d\n", ret); in imx_uart_probe()
2463 imx_uart_ports[sport->port.line] = sport; in imx_uart_probe()
2467 return uart_add_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_probe()
2474 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port); in imx_uart_remove()
2481 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_restore_context()
2482 if (!sport->context_saved) { in imx_uart_restore_context()
2483 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2487 imx_uart_writel(sport, sport->saved_reg[4], UFCR); in imx_uart_restore_context()
2488 imx_uart_writel(sport, sport->saved_reg[5], UESC); in imx_uart_restore_context()
2489 imx_uart_writel(sport, sport->saved_reg[6], UTIM); in imx_uart_restore_context()
2490 imx_uart_writel(sport, sport->saved_reg[7], UBIR); in imx_uart_restore_context()
2491 imx_uart_writel(sport, sport->saved_reg[8], UBMR); in imx_uart_restore_context()
2492 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS); in imx_uart_restore_context()
2493 imx_uart_writel(sport, sport->saved_reg[0], UCR1); in imx_uart_restore_context()
2494 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2); in imx_uart_restore_context()
2495 imx_uart_writel(sport, sport->saved_reg[2], UCR3); in imx_uart_restore_context()
2496 imx_uart_writel(sport, sport->saved_reg[3], UCR4); in imx_uart_restore_context()
2497 sport->context_saved = false; in imx_uart_restore_context()
2498 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_restore_context()
2506 spin_lock_irqsave(&sport->port.lock, flags); in imx_uart_save_context()
2507 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); in imx_uart_save_context()
2508 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); in imx_uart_save_context()
2509 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); in imx_uart_save_context()
2510 sport->saved_reg[3] = imx_uart_readl(sport, UCR4); in imx_uart_save_context()
2511 sport->saved_reg[4] = imx_uart_readl(sport, UFCR); in imx_uart_save_context()
2512 sport->saved_reg[5] = imx_uart_readl(sport, UESC); in imx_uart_save_context()
2513 sport->saved_reg[6] = imx_uart_readl(sport, UTIM); in imx_uart_save_context()
2514 sport->saved_reg[7] = imx_uart_readl(sport, UBIR); in imx_uart_save_context()
2515 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); in imx_uart_save_context()
2516 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); in imx_uart_save_context()
2517 sport->context_saved = true; in imx_uart_save_context()
2518 spin_unlock_irqrestore(&sport->port.lock, flags); in imx_uart_save_context()
2534 if (sport->have_rtscts) { in imx_uart_enable_wakeup()
2550 clk_disable(sport->clk_ipg); in imx_uart_suspend_noirq()
2564 ret = clk_enable(sport->clk_ipg); in imx_uart_resume_noirq()
2578 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_suspend()
2579 disable_irq(sport->port.irq); in imx_uart_suspend()
2581 ret = clk_prepare_enable(sport->clk_ipg); in imx_uart_suspend()
2598 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_resume()
2599 enable_irq(sport->port.irq); in imx_uart_resume()
2601 clk_disable_unprepare(sport->clk_ipg); in imx_uart_resume()
2610 uart_suspend_port(&imx_uart_uart_driver, &sport->port); in imx_uart_freeze()
2612 return clk_prepare_enable(sport->clk_ipg); in imx_uart_freeze()
2619 uart_resume_port(&imx_uart_uart_driver, &sport->port); in imx_uart_thaw()
2621 clk_disable_unprepare(sport->clk_ipg); in imx_uart_thaw()
2644 .name = "imx-uart",
2676 MODULE_ALIAS("platform:imx-uart");