Lines Matching +full:auto +full:- +full:baud
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
10 #include <linux/dma-mapping.h>
23 /* All registers are 8-bit width */
112 /* 32-bit register definition */
225 #define DRIVER_NAME "fsl-lpuart"
305 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
306 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
307 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
308 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
309 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
319 return (sport->devtype == LS1021A_LPUART || in is_layerscape_lpuart()
320 sport->devtype == LS1028A_LPUART); in is_layerscape_lpuart()
325 return sport->devtype == IMX8QXP_LPUART; in is_imx8qxp_lpuart()
330 switch (port->iotype) { in lpuart32_read()
332 return readl(port->membase + off); in lpuart32_read()
334 return ioread32be(port->membase + off); in lpuart32_read()
343 switch (port->iotype) { in lpuart32_write()
345 writel(val, port->membase + off); in lpuart32_write()
348 iowrite32be(val, port->membase + off); in lpuart32_write()
358 ret = clk_prepare_enable(sport->ipg_clk); in __lpuart_enable_clks()
362 ret = clk_prepare_enable(sport->baud_clk); in __lpuart_enable_clks()
364 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
368 clk_disable_unprepare(sport->baud_clk); in __lpuart_enable_clks()
369 clk_disable_unprepare(sport->ipg_clk); in __lpuart_enable_clks()
378 return clk_get_rate(sport->baud_clk); in lpuart_get_baud_clk_rate()
380 return clk_get_rate(sport->ipg_clk); in lpuart_get_baud_clk_rate()
390 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
392 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
408 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
409 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
422 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_dma_tx()
423 struct scatterlist *sgl = sport->tx_sgl; in lpuart_dma_tx()
424 struct device *dev = sport->port.dev; in lpuart_dma_tx()
425 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx()
428 if (sport->dma_tx_in_progress) in lpuart_dma_tx()
431 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); in lpuart_dma_tx()
433 if (xmit->tail < xmit->head || xmit->head == 0) { in lpuart_dma_tx()
434 sport->dma_tx_nents = 1; in lpuart_dma_tx()
435 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); in lpuart_dma_tx()
437 sport->dma_tx_nents = 2; in lpuart_dma_tx()
439 sg_set_buf(sgl, xmit->buf + xmit->tail, in lpuart_dma_tx()
440 UART_XMIT_SIZE - xmit->tail); in lpuart_dma_tx()
441 sg_set_buf(sgl + 1, xmit->buf, xmit->head); in lpuart_dma_tx()
444 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
451 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, in lpuart_dma_tx()
454 if (!sport->dma_tx_desc) { in lpuart_dma_tx()
455 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx()
461 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; in lpuart_dma_tx()
462 sport->dma_tx_desc->callback_param = sport; in lpuart_dma_tx()
463 sport->dma_tx_in_progress = true; in lpuart_dma_tx()
464 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); in lpuart_dma_tx()
470 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); in lpuart_stopped_or_empty()
476 struct scatterlist *sgl = &sport->tx_sgl[0]; in lpuart_dma_tx_complete()
477 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_dma_tx_complete()
478 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_dma_tx_complete()
481 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_dma_tx_complete()
483 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, in lpuart_dma_tx_complete()
486 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); in lpuart_dma_tx_complete()
488 sport->port.icount.tx += sport->dma_tx_bytes; in lpuart_dma_tx_complete()
489 sport->dma_tx_in_progress = false; in lpuart_dma_tx_complete()
490 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
493 uart_write_wakeup(&sport->port); in lpuart_dma_tx_complete()
495 if (waitqueue_active(&sport->dma_wait)) { in lpuart_dma_tx_complete()
496 wake_up(&sport->dma_wait); in lpuart_dma_tx_complete()
500 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_dma_tx_complete()
502 if (!lpuart_stopped_or_empty(&sport->port)) in lpuart_dma_tx_complete()
505 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_dma_tx_complete()
510 switch (sport->port.iotype) { in lpuart_dma_datareg_addr()
512 return sport->port.mapbase + UARTDATA; in lpuart_dma_datareg_addr()
514 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; in lpuart_dma_datareg_addr()
516 return sport->port.mapbase + UARTDR; in lpuart_dma_datareg_addr()
530 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); in lpuart_dma_tx_request()
533 dev_err(sport->port.dev, in lpuart_dma_tx_request()
543 return sport->port.iotype == UPIO_MEM32 || in lpuart_is_32()
544 sport->port.iotype == UPIO_MEM32BE; in lpuart_is_32()
550 struct dma_chan *chan = sport->dma_tx_chan; in lpuart_flush_buffer()
553 if (sport->lpuart_dma_tx_use) { in lpuart_flush_buffer()
554 if (sport->dma_tx_in_progress) { in lpuart_flush_buffer()
555 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], in lpuart_flush_buffer()
556 sport->dma_tx_nents, DMA_TO_DEVICE); in lpuart_flush_buffer()
557 sport->dma_tx_in_progress = false; in lpuart_flush_buffer()
563 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart_flush_buffer()
565 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart_flush_buffer()
567 val = readb(sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
569 writeb(val, sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
576 while (!(readb(port->membase + offset) & bit)) in lpuart_wait_bit_set()
596 sport->port.fifosize = 0; in lpuart_poll_init()
598 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_poll_init()
600 writeb(0, sport->port.membase + UARTCR2); in lpuart_poll_init()
602 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_poll_init()
605 sport->port.membase + UARTPFIFO); in lpuart_poll_init()
609 sport->port.membase + UARTCFIFO); in lpuart_poll_init()
612 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_poll_init()
613 readb(sport->port.membase + UARTDR); in lpuart_poll_init()
614 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_poll_init()
617 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_poll_init()
618 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_poll_init()
621 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); in lpuart_poll_init()
622 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_poll_init()
631 writeb(c, port->membase + UARTDR); in lpuart_poll_put_char()
636 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) in lpuart_poll_get_char()
639 return readb(port->membase + UARTDR); in lpuart_poll_get_char()
648 sport->port.fifosize = 0; in lpuart32_poll_init()
650 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_poll_init()
653 lpuart32_write(&sport->port, 0, UARTCTRL); in lpuart32_poll_init()
655 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_poll_init()
658 lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO); in lpuart32_poll_init()
661 lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO); in lpuart32_poll_init()
664 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { in lpuart32_poll_init()
665 lpuart32_read(&sport->port, UARTDATA); in lpuart32_poll_init()
666 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO); in lpuart32_poll_init()
670 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); in lpuart32_poll_init()
671 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_poll_init()
693 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart_transmit_buffer()
695 if (sport->port.x_char) { in lpuart_transmit_buffer()
696 writeb(sport->port.x_char, sport->port.membase + UARTDR); in lpuart_transmit_buffer()
697 sport->port.icount.tx++; in lpuart_transmit_buffer()
698 sport->port.x_char = 0; in lpuart_transmit_buffer()
702 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart_transmit_buffer()
703 lpuart_stop_tx(&sport->port); in lpuart_transmit_buffer()
708 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { in lpuart_transmit_buffer()
709 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); in lpuart_transmit_buffer()
710 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in lpuart_transmit_buffer()
711 sport->port.icount.tx++; in lpuart_transmit_buffer()
715 uart_write_wakeup(&sport->port); in lpuart_transmit_buffer()
718 lpuart_stop_tx(&sport->port); in lpuart_transmit_buffer()
723 struct circ_buf *xmit = &sport->port.state->xmit; in lpuart32_transmit_buffer()
726 if (sport->port.x_char) { in lpuart32_transmit_buffer()
727 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); in lpuart32_transmit_buffer()
728 sport->port.icount.tx++; in lpuart32_transmit_buffer()
729 sport->port.x_char = 0; in lpuart32_transmit_buffer()
733 if (lpuart_stopped_or_empty(&sport->port)) { in lpuart32_transmit_buffer()
734 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
738 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
741 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { in lpuart32_transmit_buffer()
742 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); in lpuart32_transmit_buffer()
743 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in lpuart32_transmit_buffer()
744 sport->port.icount.tx++; in lpuart32_transmit_buffer()
745 txcnt = lpuart32_read(&sport->port, UARTWATER); in lpuart32_transmit_buffer()
751 uart_write_wakeup(&sport->port); in lpuart32_transmit_buffer()
754 lpuart32_stop_tx(&sport->port); in lpuart32_transmit_buffer()
763 temp = readb(port->membase + UARTCR2); in lpuart_start_tx()
764 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); in lpuart_start_tx()
766 if (sport->lpuart_dma_tx_use) { in lpuart_start_tx()
770 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) in lpuart_start_tx()
780 if (sport->lpuart_dma_tx_use) { in lpuart32_start_tx()
797 unsigned char sr1 = readb(port->membase + UARTSR1); in lpuart_tx_empty()
798 unsigned char sfifo = readb(port->membase + UARTSFIFO); in lpuart_tx_empty()
800 if (sport->dma_tx_in_progress) in lpuart_tx_empty()
816 if (sport->dma_tx_in_progress) in lpuart32_tx_empty()
829 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_txint()
831 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_txint()
837 struct tty_port *port = &sport->port.state->port; in lpuart_rxint()
841 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_rxint()
843 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { in lpuart_rxint()
845 sport->port.icount.rx++; in lpuart_rxint()
850 sr = readb(sport->port.membase + UARTSR1); in lpuart_rxint()
851 rx = readb(sport->port.membase + UARTDR); in lpuart_rxint()
853 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in lpuart_rxint()
858 sport->port.icount.parity++; in lpuart_rxint()
860 sport->port.icount.frame++; in lpuart_rxint()
865 if (sr & sport->port.ignore_status_mask) { in lpuart_rxint()
871 sr &= sport->port.read_status_mask; in lpuart_rxint()
881 sport->port.sysrq = 0; in lpuart_rxint()
889 sport->port.icount.overrun += overrun; in lpuart_rxint()
895 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_rxint()
896 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); in lpuart_rxint()
899 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_rxint()
908 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_txint()
910 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_txint()
916 struct tty_port *port = &sport->port.state->port; in lpuart32_rxint()
920 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_rxint()
922 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { in lpuart32_rxint()
924 sport->port.icount.rx++; in lpuart32_rxint()
929 sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_rxint()
930 rx = lpuart32_read(&sport->port, UARTDATA); in lpuart32_rxint()
933 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) in lpuart32_rxint()
938 sport->port.icount.parity++; in lpuart32_rxint()
940 sport->port.icount.frame++; in lpuart32_rxint()
943 sport->port.icount.overrun++; in lpuart32_rxint()
945 if (sr & sport->port.ignore_status_mask) { in lpuart32_rxint()
951 sr &= sport->port.read_status_mask; in lpuart32_rxint()
961 sport->port.sysrq = 0; in lpuart32_rxint()
968 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_rxint()
978 sts = readb(sport->port.membase + UARTSR1); in lpuart_int()
981 if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) { in lpuart_int()
982 readb(sport->port.membase + UARTDR); in lpuart_int()
983 uart_handle_break(&sport->port); in lpuart_int()
985 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); in lpuart_int()
989 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) in lpuart_int()
992 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) in lpuart_int()
1003 sts = lpuart32_read(&sport->port, UARTSTAT); in lpuart32_int()
1004 rxcount = lpuart32_read(&sport->port, UARTWATER); in lpuart32_int()
1007 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) in lpuart32_int()
1010 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) in lpuart32_int()
1013 lpuart32_write(&sport->port, sts, UARTSTAT); in lpuart32_int()
1021 while (count--) { in lpuart_handle_sysrq_chars()
1030 struct circ_buf *ring = &sport->rx_ring; in lpuart_handle_sysrq()
1033 if (ring->head < ring->tail) { in lpuart_handle_sysrq()
1034 count = sport->rx_sgl.length - ring->tail; in lpuart_handle_sysrq()
1035 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1036 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1037 ring->tail = 0; in lpuart_handle_sysrq()
1040 if (ring->head > ring->tail) { in lpuart_handle_sysrq()
1041 count = ring->head - ring->tail; in lpuart_handle_sysrq()
1042 lpuart_handle_sysrq_chars(&sport->port, in lpuart_handle_sysrq()
1043 ring->buf + ring->tail, count); in lpuart_handle_sysrq()
1044 ring->tail = ring->head; in lpuart_handle_sysrq()
1050 struct tty_port *port = &sport->port.state->port; in lpuart_copy_rx_to_tty()
1053 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_copy_rx_to_tty()
1054 struct circ_buf *ring = &sport->rx_ring; in lpuart_copy_rx_to_tty()
1059 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); in lpuart_copy_rx_to_tty()
1063 lpuart32_read(&sport->port, UARTDATA); in lpuart_copy_rx_to_tty()
1066 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1068 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1071 unsigned char sr = readb(sport->port.membase + UARTSR1); in lpuart_copy_rx_to_tty()
1077 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1079 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1082 readb(sport->port.membase + UARTDR); in lpuart_copy_rx_to_tty()
1085 sport->port.icount.parity++; in lpuart_copy_rx_to_tty()
1087 sport->port.icount.frame++; in lpuart_copy_rx_to_tty()
1097 if (readb(sport->port.membase + UARTSFIFO) & in lpuart_copy_rx_to_tty()
1100 sport->port.membase + UARTSFIFO); in lpuart_copy_rx_to_tty()
1102 sport->port.membase + UARTCFIFO); in lpuart_copy_rx_to_tty()
1106 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_copy_rx_to_tty()
1110 async_tx_ack(sport->dma_rx_desc); in lpuart_copy_rx_to_tty()
1112 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1114 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); in lpuart_copy_rx_to_tty()
1116 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); in lpuart_copy_rx_to_tty()
1117 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1122 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1126 * ring->head points to the end of data already written by the DMA. in lpuart_copy_rx_to_tty()
1127 * ring->tail points to the beginning of data to be read by the in lpuart_copy_rx_to_tty()
1132 ring->head = sport->rx_sgl.length - state.residue; in lpuart_copy_rx_to_tty()
1133 BUG_ON(ring->head > sport->rx_sgl.length); in lpuart_copy_rx_to_tty()
1138 if (sport->port.sysrq) { in lpuart_copy_rx_to_tty()
1144 * At this point ring->head may point to the first byte right after the in lpuart_copy_rx_to_tty()
1146 * 0 <= ring->head <= sport->rx_sgl.length in lpuart_copy_rx_to_tty()
1148 * However ring->tail must always points inside the dma buffer: in lpuart_copy_rx_to_tty()
1149 * 0 <= ring->tail <= sport->rx_sgl.length - 1 in lpuart_copy_rx_to_tty()
1155 if (ring->head < ring->tail) { in lpuart_copy_rx_to_tty()
1156 count = sport->rx_sgl.length - ring->tail; in lpuart_copy_rx_to_tty()
1158 tty_insert_flip_string(port, ring->buf + ring->tail, count); in lpuart_copy_rx_to_tty()
1159 ring->tail = 0; in lpuart_copy_rx_to_tty()
1160 sport->port.icount.rx += count; in lpuart_copy_rx_to_tty()
1164 if (ring->tail < ring->head) { in lpuart_copy_rx_to_tty()
1165 count = ring->head - ring->tail; in lpuart_copy_rx_to_tty()
1166 tty_insert_flip_string(port, ring->buf + ring->tail, count); in lpuart_copy_rx_to_tty()
1167 /* Wrap ring->head if needed */ in lpuart_copy_rx_to_tty()
1168 if (ring->head >= sport->rx_sgl.length) in lpuart_copy_rx_to_tty()
1169 ring->head = 0; in lpuart_copy_rx_to_tty()
1170 ring->tail = ring->head; in lpuart_copy_rx_to_tty()
1171 sport->port.icount.rx += count; in lpuart_copy_rx_to_tty()
1175 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, in lpuart_copy_rx_to_tty()
1178 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_copy_rx_to_tty()
1181 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); in lpuart_copy_rx_to_tty()
1201 struct circ_buf *ring = &sport->rx_ring; in lpuart_start_rx_dma()
1203 int bits, baud; in lpuart_start_rx_dma() local
1204 struct tty_port *port = &sport->port.state->port; in lpuart_start_rx_dma()
1205 struct tty_struct *tty = port->tty; in lpuart_start_rx_dma()
1206 struct ktermios *termios = &tty->termios; in lpuart_start_rx_dma()
1207 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_start_rx_dma()
1209 baud = tty_get_baud_rate(tty); in lpuart_start_rx_dma()
1211 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; in lpuart_start_rx_dma()
1212 if (termios->c_cflag & PARENB) in lpuart_start_rx_dma()
1217 * 10ms at any baud rate. in lpuart_start_rx_dma()
1219 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; in lpuart_start_rx_dma()
1220 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); in lpuart_start_rx_dma()
1221 if (sport->rx_dma_rng_buf_len < 16) in lpuart_start_rx_dma()
1222 sport->rx_dma_rng_buf_len = 16; in lpuart_start_rx_dma()
1224 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); in lpuart_start_rx_dma()
1225 if (!ring->buf) in lpuart_start_rx_dma()
1226 return -ENOMEM; in lpuart_start_rx_dma()
1228 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); in lpuart_start_rx_dma()
1229 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, in lpuart_start_rx_dma()
1233 dev_err(sport->port.dev, "DMA Rx mapping error\n"); in lpuart_start_rx_dma()
1234 return -EINVAL; in lpuart_start_rx_dma()
1244 dev_err(sport->port.dev, in lpuart_start_rx_dma()
1249 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, in lpuart_start_rx_dma()
1250 sg_dma_address(&sport->rx_sgl), in lpuart_start_rx_dma()
1251 sport->rx_sgl.length, in lpuart_start_rx_dma()
1252 sport->rx_sgl.length / 2, in lpuart_start_rx_dma()
1255 if (!sport->dma_rx_desc) { in lpuart_start_rx_dma()
1256 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); in lpuart_start_rx_dma()
1257 return -EFAULT; in lpuart_start_rx_dma()
1260 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; in lpuart_start_rx_dma()
1261 sport->dma_rx_desc->callback_param = sport; in lpuart_start_rx_dma()
1262 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); in lpuart_start_rx_dma()
1266 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_start_rx_dma()
1268 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); in lpuart_start_rx_dma()
1270 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, in lpuart_start_rx_dma()
1271 sport->port.membase + UARTCR5); in lpuart_start_rx_dma()
1281 struct dma_chan *chan = sport->dma_rx_chan; in lpuart_dma_rx_free()
1284 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); in lpuart_dma_rx_free()
1285 kfree(sport->rx_ring.buf); in lpuart_dma_rx_free()
1286 sport->rx_ring.tail = 0; in lpuart_dma_rx_free()
1287 sport->rx_ring.head = 0; in lpuart_dma_rx_free()
1288 sport->dma_rx_desc = NULL; in lpuart_dma_rx_free()
1289 sport->dma_rx_cookie = -EINVAL; in lpuart_dma_rx_free()
1298 u8 modem = readb(sport->port.membase + UARTMODEM) & in lpuart_config_rs485()
1300 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1303 rs485->delay_rts_before_send = 0; in lpuart_config_rs485()
1304 rs485->delay_rts_after_send = 0; in lpuart_config_rs485()
1305 rs485->flags &= ~SER_RS485_RX_DURING_TX; in lpuart_config_rs485()
1307 if (rs485->flags & SER_RS485_ENABLED) { in lpuart_config_rs485()
1308 /* Enable auto RS-485 RTS mode */ in lpuart_config_rs485()
1316 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | in lpuart_config_rs485()
1318 rs485->flags |= SER_RS485_RTS_ON_SEND; in lpuart_config_rs485()
1320 if (rs485->flags & SER_RS485_RTS_ON_SEND && in lpuart_config_rs485()
1321 rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart_config_rs485()
1322 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; in lpuart_config_rs485()
1330 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart_config_rs485()
1332 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart_config_rs485()
1337 sport->port.rs485 = *rs485; in lpuart_config_rs485()
1339 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_config_rs485()
1349 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) in lpuart32_config_rs485()
1351 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1354 rs485->delay_rts_before_send = 0; in lpuart32_config_rs485()
1355 rs485->delay_rts_after_send = 0; in lpuart32_config_rs485()
1356 rs485->flags &= ~SER_RS485_RX_DURING_TX; in lpuart32_config_rs485()
1358 if (rs485->flags & SER_RS485_ENABLED) { in lpuart32_config_rs485()
1359 /* Enable auto RS-485 RTS mode */ in lpuart32_config_rs485()
1367 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | in lpuart32_config_rs485()
1369 rs485->flags |= SER_RS485_RTS_ON_SEND; in lpuart32_config_rs485()
1371 if (rs485->flags & SER_RS485_RTS_ON_SEND && in lpuart32_config_rs485()
1372 rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart32_config_rs485()
1373 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; in lpuart32_config_rs485()
1381 if (rs485->flags & SER_RS485_RTS_ON_SEND) in lpuart32_config_rs485()
1383 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) in lpuart32_config_rs485()
1388 sport->port.rs485 = *rs485; in lpuart32_config_rs485()
1390 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_config_rs485()
1399 reg = readb(port->membase + UARTMODEM); in lpuart_get_mctrl()
1431 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { in lpuart_set_mctrl()
1432 temp = readb(sport->port.membase + UARTMODEM) & in lpuart_set_mctrl()
1441 writeb(temp, port->membase + UARTMODEM); in lpuart_set_mctrl()
1454 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; in lpuart_break_ctl()
1459 writeb(temp, port->membase + UARTCR2); in lpuart_break_ctl()
1479 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1483 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1485 val = readb(sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1487 sport->port.membase + UARTPFIFO); in lpuart_setup_watermark()
1491 sport->port.membase + UARTCFIFO); in lpuart_setup_watermark()
1494 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { in lpuart_setup_watermark()
1495 readb(sport->port.membase + UARTDR); in lpuart_setup_watermark()
1496 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); in lpuart_setup_watermark()
1499 writeb(0, sport->port.membase + UARTTWFIFO); in lpuart_setup_watermark()
1500 writeb(1, sport->port.membase + UARTRWFIFO); in lpuart_setup_watermark()
1503 writeb(cr2_saved, sport->port.membase + UARTCR2); in lpuart_setup_watermark()
1512 cr2 = readb(sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1514 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_setup_watermark_enable()
1522 ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark()
1526 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_setup_watermark()
1529 val = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_setup_watermark()
1532 lpuart32_write(&sport->port, val, UARTFIFO); in lpuart32_setup_watermark()
1536 lpuart32_write(&sport->port, val, UARTWATER); in lpuart32_setup_watermark()
1539 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); in lpuart32_setup_watermark()
1548 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_setup_watermark_enable()
1550 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_setup_watermark_enable()
1555 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); in rx_dma_timer_init()
1556 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; in rx_dma_timer_init()
1557 add_timer(&sport->lpuart_timer); in rx_dma_timer_init()
1562 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); in lpuart_request_dma()
1563 if (IS_ERR(sport->dma_tx_chan)) { in lpuart_request_dma()
1564 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1566 PTR_ERR(sport->dma_tx_chan)); in lpuart_request_dma()
1567 sport->dma_tx_chan = NULL; in lpuart_request_dma()
1570 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); in lpuart_request_dma()
1571 if (IS_ERR(sport->dma_rx_chan)) { in lpuart_request_dma()
1572 dev_dbg_once(sport->port.dev, in lpuart_request_dma()
1574 PTR_ERR(sport->dma_rx_chan)); in lpuart_request_dma()
1575 sport->dma_rx_chan = NULL; in lpuart_request_dma()
1584 if (!sport->dma_tx_chan) in lpuart_tx_dma_startup()
1587 ret = lpuart_dma_tx_request(&sport->port); in lpuart_tx_dma_startup()
1591 init_waitqueue_head(&sport->dma_wait); in lpuart_tx_dma_startup()
1592 sport->lpuart_dma_tx_use = true; in lpuart_tx_dma_startup()
1594 uartbaud = lpuart32_read(&sport->port, UARTBAUD); in lpuart_tx_dma_startup()
1595 lpuart32_write(&sport->port, in lpuart_tx_dma_startup()
1598 writeb(readb(sport->port.membase + UARTCR5) | in lpuart_tx_dma_startup()
1599 UARTCR5_TDMAS, sport->port.membase + UARTCR5); in lpuart_tx_dma_startup()
1605 sport->lpuart_dma_tx_use = false; in lpuart_tx_dma_startup()
1613 if (!sport->dma_rx_chan) in lpuart_rx_dma_startup()
1621 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); in lpuart_rx_dma_startup()
1622 if (!sport->dma_rx_timeout) in lpuart_rx_dma_startup()
1623 sport->dma_rx_timeout = 1; in lpuart_rx_dma_startup()
1625 sport->lpuart_dma_rx_use = true; in lpuart_rx_dma_startup()
1628 if (sport->port.has_sysrq) { in lpuart_rx_dma_startup()
1629 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1631 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_rx_dma_startup()
1637 sport->lpuart_dma_rx_use = false; in lpuart_rx_dma_startup()
1647 temp = readb(sport->port.membase + UARTPFIFO); in lpuart_startup()
1649 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & in lpuart_startup()
1651 sport->port.fifosize = sport->txfifo_size; in lpuart_startup()
1653 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & in lpuart_startup()
1658 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_startup()
1665 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_startup()
1674 if (sport->lpuart_dma_rx_use) { in lpuart32_configure()
1676 temp = lpuart32_read(&sport->port, UARTWATER); in lpuart32_configure()
1678 lpuart32_write(&sport->port, temp, UARTWATER); in lpuart32_configure()
1680 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_configure()
1681 if (!sport->lpuart_dma_rx_use) in lpuart32_configure()
1683 if (!sport->lpuart_dma_tx_use) in lpuart32_configure()
1685 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart32_configure()
1695 temp = lpuart32_read(&sport->port, UARTFIFO); in lpuart32_startup()
1697 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & in lpuart32_startup()
1699 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1701 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & in lpuart32_startup()
1710 sport->rxfifo_size = 16; in lpuart32_startup()
1711 sport->txfifo_size = 16; in lpuart32_startup()
1712 sport->port.fifosize = sport->txfifo_size; in lpuart32_startup()
1717 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_startup()
1726 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_startup()
1732 if (sport->lpuart_dma_rx_use) { in lpuart_dma_shutdown()
1733 del_timer_sync(&sport->lpuart_timer); in lpuart_dma_shutdown()
1734 lpuart_dma_rx_free(&sport->port); in lpuart_dma_shutdown()
1737 if (sport->lpuart_dma_tx_use) { in lpuart_dma_shutdown()
1738 if (wait_event_interruptible(sport->dma_wait, in lpuart_dma_shutdown()
1739 !sport->dma_tx_in_progress) != false) { in lpuart_dma_shutdown()
1740 sport->dma_tx_in_progress = false; in lpuart_dma_shutdown()
1741 dmaengine_terminate_all(sport->dma_tx_chan); in lpuart_dma_shutdown()
1745 if (sport->dma_tx_chan) in lpuart_dma_shutdown()
1746 dma_release_channel(sport->dma_tx_chan); in lpuart_dma_shutdown()
1747 if (sport->dma_rx_chan) in lpuart_dma_shutdown()
1748 dma_release_channel(sport->dma_rx_chan); in lpuart_dma_shutdown()
1757 spin_lock_irqsave(&port->lock, flags); in lpuart_shutdown()
1760 temp = readb(port->membase + UARTCR2); in lpuart_shutdown()
1763 writeb(temp, port->membase + UARTCR2); in lpuart_shutdown()
1765 spin_unlock_irqrestore(&port->lock, flags); in lpuart_shutdown()
1777 spin_lock_irqsave(&port->lock, flags); in lpuart32_shutdown()
1785 spin_unlock_irqrestore(&port->lock, flags); in lpuart32_shutdown()
1797 unsigned int baud; in lpuart_set_termios() local
1798 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart_set_termios()
1801 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); in lpuart_set_termios()
1802 old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_set_termios()
1803 cr3 = readb(sport->port.membase + UARTCR3); in lpuart_set_termios()
1804 cr4 = readb(sport->port.membase + UARTCR4); in lpuart_set_termios()
1805 bdh = readb(sport->port.membase + UARTBDH); in lpuart_set_termios()
1806 modem = readb(sport->port.membase + UARTMODEM); in lpuart_set_termios()
1810 * - (7,e/o,1) in lpuart_set_termios()
1811 * - (8,n,1) in lpuart_set_termios()
1812 * - (8,m/s,1) in lpuart_set_termios()
1813 * - (8,e/o,1) in lpuart_set_termios()
1815 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart_set_termios()
1816 (termios->c_cflag & CSIZE) != CS7) { in lpuart_set_termios()
1817 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
1818 termios->c_cflag |= old_csize; in lpuart_set_termios()
1822 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart_set_termios()
1823 (termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
1826 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
1827 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart_set_termios()
1828 termios->c_cflag &= ~CSIZE; in lpuart_set_termios()
1829 termios->c_cflag |= CS8; in lpuart_set_termios()
1835 * When auto RS-485 RTS mode is enabled, in lpuart_set_termios()
1838 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart_set_termios()
1839 termios->c_cflag &= ~CRTSCTS; in lpuart_set_termios()
1841 if (termios->c_cflag & CRTSCTS) in lpuart_set_termios()
1846 termios->c_cflag &= ~CSTOPB; in lpuart_set_termios()
1848 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart_set_termios()
1849 if ((termios->c_cflag & CSIZE) == CS7) in lpuart_set_termios()
1850 termios->c_cflag |= PARENB; in lpuart_set_termios()
1852 if (termios->c_cflag & PARENB) { in lpuart_set_termios()
1853 if (termios->c_cflag & CMSPAR) { in lpuart_set_termios()
1855 if (termios->c_cflag & PARODD) in lpuart_set_termios()
1861 if ((termios->c_cflag & CSIZE) == CS8) in lpuart_set_termios()
1863 if (termios->c_cflag & PARODD) in lpuart_set_termios()
1873 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); in lpuart_set_termios()
1877 * baud rate and restart Rx DMA path. in lpuart_set_termios()
1879 * Since timer function acqures sport->port.lock, need to stop before in lpuart_set_termios()
1882 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
1883 del_timer_sync(&sport->lpuart_timer); in lpuart_set_termios()
1884 lpuart_dma_rx_free(&sport->port); in lpuart_set_termios()
1887 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_set_termios()
1889 sport->port.read_status_mask = 0; in lpuart_set_termios()
1890 if (termios->c_iflag & INPCK) in lpuart_set_termios()
1891 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; in lpuart_set_termios()
1892 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart_set_termios()
1893 sport->port.read_status_mask |= UARTSR1_FE; in lpuart_set_termios()
1896 sport->port.ignore_status_mask = 0; in lpuart_set_termios()
1897 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
1898 sport->port.ignore_status_mask |= UARTSR1_PE; in lpuart_set_termios()
1899 if (termios->c_iflag & IGNBRK) { in lpuart_set_termios()
1900 sport->port.ignore_status_mask |= UARTSR1_FE; in lpuart_set_termios()
1905 if (termios->c_iflag & IGNPAR) in lpuart_set_termios()
1906 sport->port.ignore_status_mask |= UARTSR1_OR; in lpuart_set_termios()
1909 /* update the per-port timeout */ in lpuart_set_termios()
1910 uart_update_timeout(port, termios->c_cflag, baud); in lpuart_set_termios()
1913 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_set_termios()
1917 sport->port.membase + UARTCR2); in lpuart_set_termios()
1919 sbr = sport->port.uartclk / (16 * baud); in lpuart_set_termios()
1920 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; in lpuart_set_termios()
1925 writeb(cr4 | brfa, sport->port.membase + UARTCR4); in lpuart_set_termios()
1926 writeb(bdh, sport->port.membase + UARTBDH); in lpuart_set_termios()
1927 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); in lpuart_set_termios()
1928 writeb(cr3, sport->port.membase + UARTCR3); in lpuart_set_termios()
1929 writeb(cr1, sport->port.membase + UARTCR1); in lpuart_set_termios()
1930 writeb(modem, sport->port.membase + UARTMODEM); in lpuart_set_termios()
1933 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_set_termios()
1935 if (old && sport->lpuart_dma_rx_use) { in lpuart_set_termios()
1939 sport->lpuart_dma_rx_use = false; in lpuart_set_termios()
1942 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_set_termios()
1950 u32 clk = port->uartclk; in __lpuart32_serial_setbrg()
1953 * The idea is to use the best OSR (over-sampling rate) possible. in __lpuart32_serial_setbrg()
1954 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. in __lpuart32_serial_setbrg()
1959 * Baud Rate = baud clock / ((OSR+1) × SBR) in __lpuart32_serial_setbrg()
1972 * calculate the baud rate difference based on the temporary in __lpuart32_serial_setbrg()
1975 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; in __lpuart32_serial_setbrg()
1979 if (tmp_diff > (baudrate - tmp)) { in __lpuart32_serial_setbrg()
1980 tmp_diff = baudrate - tmp; in __lpuart32_serial_setbrg()
1999 dev_warn(port->dev, in __lpuart32_serial_setbrg()
2000 "unacceptable baud rate difference of more than 3%%\n"); in __lpuart32_serial_setbrg()
2008 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; in __lpuart32_serial_setbrg()
2024 __lpuart32_serial_setbrg(&sport->port, baudrate, in lpuart32_serial_setbrg()
2025 sport->lpuart_dma_rx_use, in lpuart32_serial_setbrg()
2026 sport->lpuart_dma_tx_use); in lpuart32_serial_setbrg()
2037 unsigned int baud; in lpuart32_set_termios() local
2038 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; in lpuart32_set_termios()
2040 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_set_termios()
2041 modem = lpuart32_read(&sport->port, UARTMODIR); in lpuart32_set_termios()
2045 * - (7,e/o,1) in lpuart32_set_termios()
2046 * - (8,n,1) in lpuart32_set_termios()
2047 * - (8,m/s,1) in lpuart32_set_termios()
2048 * - (8,e/o,1) in lpuart32_set_termios()
2050 while ((termios->c_cflag & CSIZE) != CS8 && in lpuart32_set_termios()
2051 (termios->c_cflag & CSIZE) != CS7) { in lpuart32_set_termios()
2052 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2053 termios->c_cflag |= old_csize; in lpuart32_set_termios()
2057 if ((termios->c_cflag & CSIZE) == CS8 || in lpuart32_set_termios()
2058 (termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2061 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2062 if ((termios->c_cflag & CSIZE) != CS8) { in lpuart32_set_termios()
2063 termios->c_cflag &= ~CSIZE; in lpuart32_set_termios()
2064 termios->c_cflag |= CS8; in lpuart32_set_termios()
2070 * When auto RS-485 RTS mode is enabled, in lpuart32_set_termios()
2073 if (sport->port.rs485.flags & SER_RS485_ENABLED) in lpuart32_set_termios()
2074 termios->c_cflag &= ~CRTSCTS; in lpuart32_set_termios()
2076 if (termios->c_cflag & CRTSCTS) { in lpuart32_set_termios()
2079 termios->c_cflag &= ~CRTSCTS; in lpuart32_set_termios()
2083 if (termios->c_cflag & CSTOPB) in lpuart32_set_termios()
2084 termios->c_cflag &= ~CSTOPB; in lpuart32_set_termios()
2086 /* parity must be enabled when CS7 to match 8-bits format */ in lpuart32_set_termios()
2087 if ((termios->c_cflag & CSIZE) == CS7) in lpuart32_set_termios()
2088 termios->c_cflag |= PARENB; in lpuart32_set_termios()
2090 if ((termios->c_cflag & PARENB)) { in lpuart32_set_termios()
2091 if (termios->c_cflag & CMSPAR) { in lpuart32_set_termios()
2096 if ((termios->c_cflag & CSIZE) == CS8) in lpuart32_set_termios()
2098 if (termios->c_cflag & PARODD) in lpuart32_set_termios()
2108 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); in lpuart32_set_termios()
2112 * baud rate and restart Rx DMA path. in lpuart32_set_termios()
2114 * Since timer function acqures sport->port.lock, need to stop before in lpuart32_set_termios()
2117 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2118 del_timer_sync(&sport->lpuart_timer); in lpuart32_set_termios()
2119 lpuart_dma_rx_free(&sport->port); in lpuart32_set_termios()
2122 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_set_termios()
2124 sport->port.read_status_mask = 0; in lpuart32_set_termios()
2125 if (termios->c_iflag & INPCK) in lpuart32_set_termios()
2126 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; in lpuart32_set_termios()
2127 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in lpuart32_set_termios()
2128 sport->port.read_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2131 sport->port.ignore_status_mask = 0; in lpuart32_set_termios()
2132 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2133 sport->port.ignore_status_mask |= UARTSTAT_PE; in lpuart32_set_termios()
2134 if (termios->c_iflag & IGNBRK) { in lpuart32_set_termios()
2135 sport->port.ignore_status_mask |= UARTSTAT_FE; in lpuart32_set_termios()
2140 if (termios->c_iflag & IGNPAR) in lpuart32_set_termios()
2141 sport->port.ignore_status_mask |= UARTSTAT_OR; in lpuart32_set_termios()
2144 /* update the per-port timeout */ in lpuart32_set_termios()
2145 uart_update_timeout(port, termios->c_cflag, baud); in lpuart32_set_termios()
2148 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_set_termios()
2151 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), in lpuart32_set_termios()
2154 lpuart32_serial_setbrg(sport, baud); in lpuart32_set_termios()
2155 lpuart32_write(&sport->port, modem, UARTMODIR); in lpuart32_set_termios()
2156 lpuart32_write(&sport->port, ctrl, UARTCTRL); in lpuart32_set_termios()
2159 if (old && sport->lpuart_dma_rx_use) { in lpuart32_set_termios()
2163 sport->lpuart_dma_rx_use = false; in lpuart32_set_termios()
2166 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_set_termios()
2188 port->type = PORT_LPUART; in lpuart_config_port()
2195 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) in lpuart_verify_port()
2196 ret = -EINVAL; in lpuart_verify_port()
2197 if (port->irq != ser->irq) in lpuart_verify_port()
2198 ret = -EINVAL; in lpuart_verify_port()
2199 if (ser->io_type != UPIO_MEM) in lpuart_verify_port()
2200 ret = -EINVAL; in lpuart_verify_port()
2201 if (port->uartclk / 16 != ser->baud_base) in lpuart_verify_port()
2202 ret = -EINVAL; in lpuart_verify_port()
2203 if (port->iobase != ser->port) in lpuart_verify_port()
2204 ret = -EINVAL; in lpuart_verify_port()
2205 if (ser->hub6 != 0) in lpuart_verify_port()
2206 ret = -EINVAL; in lpuart_verify_port()
2264 writeb(ch, port->membase + UARTDR); in lpuart_console_putchar()
2276 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart_console_write()
2281 if (sport->port.sysrq || oops_in_progress) in lpuart_console_write()
2282 locked = spin_trylock_irqsave(&sport->port.lock, flags); in lpuart_console_write()
2284 spin_lock_irqsave(&sport->port.lock, flags); in lpuart_console_write()
2287 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); in lpuart_console_write()
2290 writeb(cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2292 uart_console_write(&sport->port, s, count, lpuart_console_putchar); in lpuart_console_write()
2295 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); in lpuart_console_write()
2297 writeb(old_cr2, sport->port.membase + UARTCR2); in lpuart_console_write()
2300 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart_console_write()
2306 struct lpuart_port *sport = lpuart_ports[co->index]; in lpuart32_console_write()
2311 if (sport->port.sysrq || oops_in_progress) in lpuart32_console_write()
2312 locked = spin_trylock_irqsave(&sport->port.lock, flags); in lpuart32_console_write()
2314 spin_lock_irqsave(&sport->port.lock, flags); in lpuart32_console_write()
2317 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_write()
2320 lpuart32_write(&sport->port, cr, UARTCTRL); in lpuart32_console_write()
2322 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); in lpuart32_console_write()
2325 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); in lpuart32_console_write()
2327 lpuart32_write(&sport->port, old_cr, UARTCTRL); in lpuart32_console_write()
2330 spin_unlock_irqrestore(&sport->port.lock, flags); in lpuart32_console_write()
2338 lpuart_console_get_options(struct lpuart_port *sport, int *baud, in lpuart_console_get_options() argument
2344 cr = readb(sport->port.membase + UARTCR2); in lpuart_console_get_options()
2351 cr = readb(sport->port.membase + UARTCR1); in lpuart_console_get_options()
2366 bdh = readb(sport->port.membase + UARTBDH); in lpuart_console_get_options()
2368 bdl = readb(sport->port.membase + UARTBDL); in lpuart_console_get_options()
2372 brfa = readb(sport->port.membase + UARTCR4); in lpuart_console_get_options()
2377 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) in lpuart_console_get_options()
2381 if (*baud != baud_raw) in lpuart_console_get_options()
2382 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart_console_get_options()
2383 "from %d to %d\n", baud_raw, *baud); in lpuart_console_get_options()
2387 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, in lpuart32_console_get_options() argument
2393 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2400 cr = lpuart32_read(&sport->port, UARTCTRL); in lpuart32_console_get_options()
2415 bd = lpuart32_read(&sport->port, UARTBAUD); in lpuart32_console_get_options()
2420 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) in lpuart32_console_get_options()
2424 if (*baud != baud_raw) in lpuart32_console_get_options()
2425 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" in lpuart32_console_get_options()
2426 "from %d to %d\n", baud_raw, *baud); in lpuart32_console_get_options()
2432 int baud = 115200; in lpuart_console_setup() local
2442 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) in lpuart_console_setup()
2443 co->index = 0; in lpuart_console_setup()
2445 sport = lpuart_ports[co->index]; in lpuart_console_setup()
2447 return -ENODEV; in lpuart_console_setup()
2450 uart_parse_options(options, &baud, &parity, &bits, &flow); in lpuart_console_setup()
2453 lpuart32_console_get_options(sport, &baud, &parity, &bits); in lpuart_console_setup()
2455 lpuart_console_get_options(sport, &baud, &parity, &bits); in lpuart_console_setup()
2462 return uart_set_options(&sport->port, co, baud, parity, bits, flow); in lpuart_console_setup()
2472 .index = -1,
2482 .index = -1,
2488 struct earlycon_device *dev = con->data; in lpuart_early_write()
2490 uart_console_write(&dev->port, s, n, lpuart_console_putchar); in lpuart_early_write()
2495 struct earlycon_device *dev = con->data; in lpuart32_early_write()
2497 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); in lpuart32_early_write()
2503 if (!device->port.membase) in lpuart_early_console_setup()
2504 return -ENODEV; in lpuart_early_console_setup()
2506 device->con->write = lpuart_early_write; in lpuart_early_console_setup()
2513 if (!device->port.membase) in lpuart32_early_console_setup()
2514 return -ENODEV; in lpuart32_early_console_setup()
2516 if (device->port.iotype != UPIO_MEM32) in lpuart32_early_console_setup()
2517 device->port.iotype = UPIO_MEM32BE; in lpuart32_early_console_setup()
2519 device->con->write = lpuart32_early_write; in lpuart32_early_console_setup()
2528 if (!device->port.membase) in ls1028a_early_console_setup()
2529 return -ENODEV; in ls1028a_early_console_setup()
2531 device->port.iotype = UPIO_MEM32; in ls1028a_early_console_setup()
2532 device->con->write = lpuart32_early_write; in ls1028a_early_console_setup()
2535 if (device->port.uartclk && device->baud) in ls1028a_early_console_setup()
2536 __lpuart32_serial_setbrg(&device->port, device->baud, in ls1028a_early_console_setup()
2540 cr = lpuart32_read(&device->port, UARTCTRL); in ls1028a_early_console_setup()
2542 lpuart32_write(&device->port, cr, UARTCTRL); in ls1028a_early_console_setup()
2550 if (!device->port.membase) in lpuart32_imx_early_console_setup()
2551 return -ENODEV; in lpuart32_imx_early_console_setup()
2553 device->port.iotype = UPIO_MEM32; in lpuart32_imx_early_console_setup()
2554 device->port.membase += IMX_REG_OFF; in lpuart32_imx_early_console_setup()
2555 device->con->write = lpuart32_early_write; in lpuart32_imx_early_console_setup()
2559 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2560 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2561 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2562 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2584 &pdev->dev); in lpuart_probe()
2585 const struct lpuart_soc_data *sdata = of_id->data; in lpuart_probe()
2586 struct device_node *np = pdev->dev.of_node; in lpuart_probe()
2591 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); in lpuart_probe()
2593 return -ENOMEM; in lpuart_probe()
2596 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); in lpuart_probe()
2597 if (IS_ERR(sport->port.membase)) in lpuart_probe()
2598 return PTR_ERR(sport->port.membase); in lpuart_probe()
2600 sport->port.membase += sdata->reg_off; in lpuart_probe()
2601 sport->port.mapbase = res->start; in lpuart_probe()
2602 sport->port.dev = &pdev->dev; in lpuart_probe()
2603 sport->port.type = PORT_LPUART; in lpuart_probe()
2604 sport->devtype = sdata->devtype; in lpuart_probe()
2608 sport->port.irq = ret; in lpuart_probe()
2609 sport->port.iotype = sdata->iotype; in lpuart_probe()
2611 sport->port.ops = &lpuart32_pops; in lpuart_probe()
2613 sport->port.ops = &lpuart_pops; in lpuart_probe()
2614 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); in lpuart_probe()
2615 sport->port.flags = UPF_BOOT_AUTOCONF; in lpuart_probe()
2618 sport->port.rs485_config = lpuart32_config_rs485; in lpuart_probe()
2620 sport->port.rs485_config = lpuart_config_rs485; in lpuart_probe()
2622 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); in lpuart_probe()
2623 if (IS_ERR(sport->ipg_clk)) { in lpuart_probe()
2624 ret = PTR_ERR(sport->ipg_clk); in lpuart_probe()
2625 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); in lpuart_probe()
2629 sport->baud_clk = NULL; in lpuart_probe()
2631 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); in lpuart_probe()
2632 if (IS_ERR(sport->baud_clk)) { in lpuart_probe()
2633 ret = PTR_ERR(sport->baud_clk); in lpuart_probe()
2634 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); in lpuart_probe()
2643 dev_err(&pdev->dev, "port line is full, add device failed\n"); in lpuart_probe()
2646 sport->id_allocated = true; in lpuart_probe()
2649 dev_err(&pdev->dev, "serial%d out of range\n", ret); in lpuart_probe()
2650 ret = -EINVAL; in lpuart_probe()
2653 sport->port.line = ret; in lpuart_probe()
2658 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); in lpuart_probe()
2660 lpuart_ports[sport->port.line] = sport; in lpuart_probe()
2662 platform_set_drvdata(pdev, &sport->port); in lpuart_probe()
2666 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, in lpuart_probe()
2670 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, in lpuart_probe()
2677 ret = uart_add_one_port(&lpuart_reg, &sport->port); in lpuart_probe()
2681 ret = uart_get_rs485_mode(&sport->port); in lpuart_probe()
2685 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) in lpuart_probe()
2686 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); in lpuart_probe()
2688 if (sport->port.rs485.delay_rts_before_send || in lpuart_probe()
2689 sport->port.rs485.delay_rts_after_send) in lpuart_probe()
2690 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); in lpuart_probe()
2692 sport->port.rs485_config(&sport->port, &sport->port.rs485); in lpuart_probe()
2702 if (sport->id_allocated) in lpuart_probe()
2703 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); in lpuart_probe()
2711 uart_remove_one_port(&lpuart_reg, &sport->port); in lpuart_remove()
2713 if (sport->id_allocated) in lpuart_remove()
2714 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); in lpuart_remove()
2718 if (sport->dma_tx_chan) in lpuart_remove()
2719 dma_release_channel(sport->dma_tx_chan); in lpuart_remove()
2721 if (sport->dma_rx_chan) in lpuart_remove()
2722 dma_release_channel(sport->dma_rx_chan); in lpuart_remove()
2735 temp = lpuart32_read(&sport->port, UARTCTRL); in lpuart_suspend()
2737 lpuart32_write(&sport->port, temp, UARTCTRL); in lpuart_suspend()
2740 temp = readb(sport->port.membase + UARTCR2); in lpuart_suspend()
2742 writeb(temp, sport->port.membase + UARTCR2); in lpuart_suspend()
2745 uart_suspend_port(&lpuart_reg, &sport->port); in lpuart_suspend()
2748 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_suspend()
2750 if (sport->lpuart_dma_rx_use) { in lpuart_suspend()
2753 * non-idle DMA channels. If port wakeup is enabled or if port in lpuart_suspend()
2759 del_timer_sync(&sport->lpuart_timer); in lpuart_suspend()
2760 lpuart_dma_rx_free(&sport->port); in lpuart_suspend()
2765 temp = lpuart32_read(&sport->port, UARTBAUD); in lpuart_suspend()
2766 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, in lpuart_suspend()
2769 writeb(readb(sport->port.membase + UARTCR5) & in lpuart_suspend()
2770 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); in lpuart_suspend()
2774 if (sport->lpuart_dma_tx_use) { in lpuart_suspend()
2775 sport->dma_tx_in_progress = false; in lpuart_suspend()
2776 dmaengine_terminate_all(sport->dma_tx_chan); in lpuart_suspend()
2779 if (sport->port.suspended && !irq_wake) in lpuart_suspend()
2788 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); in lpuart_resume()
2790 if (sport->port.suspended && !irq_wake) in lpuart_resume()
2798 if (sport->lpuart_dma_rx_use) { in lpuart_resume()
2803 sport->lpuart_dma_rx_use = false; in lpuart_resume()
2812 uart_resume_port(&lpuart_reg, &sport->port); in lpuart_resume()
2823 .name = "fsl-lpuart",