57 	{ .compatible = "mrvl,pxa-uart", },
58 	{ .compatible = "mrvl,mmp-uart", },
63 /* Uart divisor latch write */
93 	struct uart_8250_port uart = {};  in serial_pxa_probe()  local
120 		uart.port.line = ret;  in serial_pxa_probe()
122 	uart.port.type = PORT_XSCALE;  in serial_pxa_probe()
123 	uart.port.iotype = UPIO_MEM32;  in serial_pxa_probe()
124 	uart.port.mapbase = mmres->start;  in serial_pxa_probe()
125 	uart.port.regshift = 2;  in serial_pxa_probe()
126 	uart.port.irq = irq;  in serial_pxa_probe()
127 	uart.port.fifosize = 64;  in serial_pxa_probe()
128 	uart.port.flags = UPF_IOREMAP | UPF_SKIP_TEST | UPF_FIXED_TYPE;  in serial_pxa_probe()
129 	uart.port.dev = &pdev->dev;  in serial_pxa_probe()
130 	uart.port.uartclk = clk_get_rate(data->clk);  in serial_pxa_probe()
131 	uart.port.pm = serial_pxa_pm;  in serial_pxa_probe()
132 	uart.port.private_data = data;  in serial_pxa_probe()
133 	uart.dl_write = serial_pxa_dl_write;  in serial_pxa_probe()
135 	ret = serial8250_register_8250_port(&uart);  in serial_pxa_probe()
166 		.name	= "pxa2xx-uart",
186 OF_EARLYCON_DECLARE(early_pxa, "mrvl,pxa-uart", early_serial_pxa_setup);
191 MODULE_ALIAS("platform:pxa2xx-uart");