Lines Matching refs:ChP
382 #define sClrBreak(ChP) \ argument
384 (ChP)->TxControl[3] &= ~SETBREAK; \
385 out32((ChP)->IndexAddr,(ChP)->TxControl); \
394 #define sClrDTR(ChP) \ argument
396 (ChP)->TxControl[3] &= ~SET_DTR; \
397 out32((ChP)->IndexAddr,(ChP)->TxControl); \
406 #define sClrRTS(ChP) \ argument
408 if ((ChP)->rtsToggle) break; \
409 (ChP)->TxControl[3] &= ~SET_RTS; \
410 out32((ChP)->IndexAddr,(ChP)->TxControl); \
419 #define sClrTxXOFF(ChP) \ argument
421 sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
422 sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
481 #define sDisCTSFlowCtl(ChP) \ argument
483 (ChP)->TxControl[2] &= ~CTSFC_EN; \
484 out32((ChP)->IndexAddr,(ChP)->TxControl); \
493 #define sDisIXANY(ChP) \ argument
495 (ChP)->R[0x0e] = 0x86; \
496 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
507 #define sDisParity(ChP) \ argument
509 (ChP)->TxControl[2] &= ~PARITY_EN; \
510 out32((ChP)->IndexAddr,(ChP)->TxControl); \
519 #define sDisRTSToggle(ChP) \ argument
521 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
522 out32((ChP)->IndexAddr,(ChP)->TxControl); \
523 (ChP)->rtsToggle = 0; \
532 #define sDisRxFIFO(ChP) \ argument
534 (ChP)->R[0x32] = 0x0a; \
535 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
547 #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0) argument
559 #define sDisTransmit(ChP) \ argument
561 (ChP)->TxControl[3] &= ~TX_ENABLE; \
562 out32((ChP)->IndexAddr,(ChP)->TxControl); \
571 #define sDisTxSoftFlowCtl(ChP) \ argument
573 (ChP)->R[0x06] = 0x8a; \
574 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
596 #define sEnCTSFlowCtl(ChP) \ argument
598 (ChP)->TxControl[2] |= CTSFC_EN; \
599 out32((ChP)->IndexAddr,(ChP)->TxControl); \
608 #define sEnIXANY(ChP) \ argument
610 (ChP)->R[0x0e] = 0x21; \
611 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
625 #define sEnParity(ChP) \ argument
627 (ChP)->TxControl[2] |= PARITY_EN; \
628 out32((ChP)->IndexAddr,(ChP)->TxControl); \
639 #define sEnRTSToggle(ChP) \ argument
641 (ChP)->RxControl[2] &= ~RTSFC_EN; \
642 out32((ChP)->IndexAddr,(ChP)->RxControl); \
643 (ChP)->TxControl[2] |= RTSTOG_EN; \
644 (ChP)->TxControl[3] &= ~SET_RTS; \
645 out32((ChP)->IndexAddr,(ChP)->TxControl); \
646 (ChP)->rtsToggle = 1; \
655 #define sEnRxFIFO(ChP) \ argument
657 (ChP)->R[0x32] = 0x08; \
658 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
676 #define sEnRxProcessor(ChP) \ argument
678 (ChP)->RxControl[2] |= RXPROC_EN; \
679 out32((ChP)->IndexAddr,(ChP)->RxControl); \
692 #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE) argument
700 #define sEnTransmit(ChP) \ argument
702 (ChP)->TxControl[3] |= TX_ENABLE; \
703 out32((ChP)->IndexAddr,(ChP)->TxControl); \
712 #define sEnTxSoftFlowCtl(ChP) \ argument
714 (ChP)->R[0x06] = 0xc5; \
715 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
754 #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA… argument
764 #define sGetChanNum(ChP) (ChP)->ChanNum argument
792 #define sGetChanStatus(ChP) sInW((ChP)->ChanStat) argument
808 #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat) argument
815 #define sGetChanRI(ChP) ((ChP)->CtlP->AltChanRingIndicator ? \
816 (sInB((ByteIO_t)((ChP)->ChanStat+8)) & DSR_ACT) : \
817 (((ChP)->CtlP->boardType == ROCKET_TYPE_PC104) ? \
818 (!(sInB((ChP)->CtlP->AiopIO[3]) & sBitMapSetTbl[(ChP)->ChanNum])) : \
861 #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount) argument
872 #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount) argument
881 #define sGetTxRxDataIO(ChP) (ChP)->TxRxData argument
892 #define sInitChanDefaults(ChP) \ argument
894 (ChP)->CtlP = NULLCTLPTR; \
895 (ChP)->AiopNum = NULLAIOP; \
896 (ChP)->ChanID = AIOPID_NULL; \
897 (ChP)->ChanNum = NULLCHAN; \
919 #define sSendBreak(ChP) \ argument
921 (ChP)->TxControl[3] |= SETBREAK; \
922 out32((ChP)->IndexAddr,(ChP)->TxControl); \
932 #define sSetBaud(ChP,DIVISOR) \ argument
934 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
935 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
936 out32((ChP)->IndexAddr,(ChP)->BaudDiv); \
945 #define sSetData7(ChP) \ argument
947 (ChP)->TxControl[2] &= ~DATA8BIT; \
948 out32((ChP)->IndexAddr,(ChP)->TxControl); \
957 #define sSetData8(ChP) \ argument
959 (ChP)->TxControl[2] |= DATA8BIT; \
960 out32((ChP)->IndexAddr,(ChP)->TxControl); \
969 #define sSetDTR(ChP) \ argument
971 (ChP)->TxControl[3] |= SET_DTR; \
972 out32((ChP)->IndexAddr,(ChP)->TxControl); \
986 #define sSetEvenParity(ChP) \ argument
988 (ChP)->TxControl[2] |= EVEN_PAR; \
989 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1003 #define sSetOddParity(ChP) \ argument
1005 (ChP)->TxControl[2] &= ~EVEN_PAR; \
1006 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1015 #define sSetRTS(ChP) \ argument
1017 if ((ChP)->rtsToggle) break; \
1018 (ChP)->TxControl[3] |= SET_RTS; \
1019 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1041 #define sSetRxTrigger(ChP,LEVEL) \ argument
1043 (ChP)->RxControl[2] &= ~TRIG_MASK; \
1044 (ChP)->RxControl[2] |= LEVEL; \
1045 out32((ChP)->IndexAddr,(ChP)->RxControl); \
1054 #define sSetStop1(ChP) \ argument
1056 (ChP)->TxControl[2] &= ~STOP2; \
1057 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1066 #define sSetStop2(ChP) \ argument
1068 (ChP)->TxControl[2] |= STOP2; \
1069 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1079 #define sSetTxXOFFChar(ChP,CH) \ argument
1081 (ChP)->R[0x07] = (CH); \
1082 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
1092 #define sSetTxXONChar(ChP,CH) \ argument
1094 (ChP)->R[0x0b] = (CH); \
1095 out32((ChP)->IndexAddr,&(ChP)->R[0x08]); \
1108 #define sStartRxProcessor(ChP) out32((ChP)->IndexAddr,&(ChP)->R[0]) argument