Lines Matching +full:cts +full:- +full:rts +full:- +full:swap
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * rocket_int.h --- internal header file for rocket.c
34 * byte-swapping the I/O instructions. However, all accesses using
35 * sOutDW aren't really 32-bit accesses, but should be handled in byte
36 * order. Hence the use of the cpu_to_le32() macro to byte-swap
37 * things to no-op the byte swapping done by the big-endian outl()
93 #define CTLID_NULL -1 /* no controller exists */
97 #define AIOPID_NULL -1 /* no AIOP or channel exists */
101 Global Register Offsets - Direct Access - Fixed values
112 Channel Register Offsets for 1st channel in AIOP - Direct Access
121 Tx Control Register Offsets - Indexed - External - Fixed
126 #define _TXREP1B1 0x98A /* Tx Replace Value #1 - Byte 1 8 Read / Write */
127 #define _TXREP1B2 0x98B /* Tx Replace Value #1 - Byte 2 8 Read / Write */
131 Memory Controller Register Offsets - Indexed - External - Fixed
147 Tx Priority Buffer - Indexed - External - Fixed
153 Channel Register Offsets - Indexed - Internal - Fixed
172 #define CTS_ACT 0x20 /* CTS input asserted */
189 #define CTSFC_EN 0x80 /* CTS flow control enable bit */
190 #define RTSTOG_EN 0x40 /* RTS toggle enable bit */
200 #define SET_RTS 0x02 /* assert RTS */
203 #define RTSFC_EN 0x40 /* RTS flow control enable */
218 #define DELTA_CTS 0x02 /* CTS change interrupt */
384 (ChP)->TxControl[3] &= ~SETBREAK; \
385 out32((ChP)->IndexAddr,(ChP)->TxControl); \
396 (ChP)->TxControl[3] &= ~SET_DTR; \
397 out32((ChP)->IndexAddr,(ChP)->TxControl); \
402 Purpose: Clr the RTS output
408 if ((ChP)->rtsToggle) break; \
409 (ChP)->TxControl[3] &= ~SET_RTS; \
410 out32((ChP)->IndexAddr,(ChP)->TxControl); \
421 sOutB((ChP)->Cmd,TXOVERIDE | (Byte_t)(ChP)->ChanNum); \
422 sOutB((ChP)->Cmd,(Byte_t)(ChP)->ChanNum); \
440 #define sControllerEOI(CTLP) sOutB((CTLP)->MReg2IO,(CTLP)->MReg2 | INT_STROB)
452 if ((CTLP)->isUPCI) { \
453 Word_t w = sInW((CTLP)->PCIIO); \
454 sOutW((CTLP)->PCIIO, (w ^ PCI_INT_CTRL_AIOP)); \
455 sOutW((CTLP)->PCIIO, w); \
458 sOutW((CTLP)->PCIIO, PCI_STROB); \
471 (CTLP)->MReg3 &= sBitMapClrTbl[AIOPNUM]; \
472 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
477 Purpose: Disable output flow control using CTS
483 (ChP)->TxControl[2] &= ~CTSFC_EN; \
484 out32((ChP)->IndexAddr,(ChP)->TxControl); \
495 (ChP)->R[0x0e] = 0x86; \
496 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
509 (ChP)->TxControl[2] &= ~PARITY_EN; \
510 out32((ChP)->IndexAddr,(ChP)->TxControl); \
515 Purpose: Disable RTS toggle
521 (ChP)->TxControl[2] &= ~RTSTOG_EN; \
522 out32((ChP)->IndexAddr,(ChP)->TxControl); \
523 (ChP)->rtsToggle = 0; \
534 (ChP)->R[0x32] = 0x0a; \
535 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
547 #define sDisRxStatusMode(ChP) sOutW((ChP)->ChanStat,0)
561 (ChP)->TxControl[3] &= ~TX_ENABLE; \
562 out32((ChP)->IndexAddr,(ChP)->TxControl); \
573 (ChP)->R[0x06] = 0x8a; \
574 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
586 (CTLP)->MReg3 |= sBitMapSetTbl[AIOPNUM]; \
587 sOutB((CTLP)->MReg3IO,(CTLP)->MReg3); \
592 Purpose: Enable output flow control using CTS
598 (ChP)->TxControl[2] |= CTSFC_EN; \
599 out32((ChP)->IndexAddr,(ChP)->TxControl); \
610 (ChP)->R[0x0e] = 0x21; \
611 out32((ChP)->IndexAddr,&(ChP)->R[0x0c]); \
627 (ChP)->TxControl[2] |= PARITY_EN; \
628 out32((ChP)->IndexAddr,(ChP)->TxControl); \
633 Purpose: Enable RTS toggle
636 Comments: This function will disable RTS flow control and clear the RTS
637 line to allow operation of RTS toggle.
641 (ChP)->RxControl[2] &= ~RTSFC_EN; \
642 out32((ChP)->IndexAddr,(ChP)->RxControl); \
643 (ChP)->TxControl[2] |= RTSTOG_EN; \
644 (ChP)->TxControl[3] &= ~SET_RTS; \
645 out32((ChP)->IndexAddr,(ChP)->TxControl); \
646 (ChP)->rtsToggle = 1; \
657 (ChP)->R[0x32] = 0x08; \
658 out32((ChP)->IndexAddr,&(ChP)->R[0x30]); \
678 (ChP)->RxControl[2] |= RXPROC_EN; \
679 out32((ChP)->IndexAddr,(ChP)->RxControl); \
692 #define sEnRxStatusMode(ChP) sOutW((ChP)->ChanStat,STATMODE)
702 (ChP)->TxControl[3] |= TX_ENABLE; \
703 out32((ChP)->IndexAddr,(ChP)->TxControl); \
714 (ChP)->R[0x06] = 0xc5; \
715 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
728 #define sGetAiopIntStatus(CTLP,AIOPNUM) sInB((CTLP)->AiopIntChanIO[AIOPNUM])
738 #define sGetAiopNumChan(CTLP,AIOPNUM) (CTLP)->AiopNumChan[AIOPNUM]
751 DELTA_CTS: CTS change interrupt
754 #define sGetChanIntID(ChP) (sInB((ChP)->IntID) & (RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA…
764 #define sGetChanNum(ChP) (ChP)->ChanNum
774 CTS_ACT: CTS input asserted
792 #define sGetChanStatus(ChP) sInW((ChP)->ChanStat)
801 CTS_ACT: CTS input asserted
808 #define sGetChanStatusLo(ChP) sInB((ByteIO_t)(ChP)->ChanStat)
812 * Defined as a function in rocket.c -aes
815 #define sGetChanRI(ChP) ((ChP)->CtlP->AltChanRingIndicator ? \
816 (sInB((ByteIO_t)((ChP)->ChanStat+8)) & DSR_ACT) : \
817 (((ChP)->CtlP->boardType == ROCKET_TYPE_PC104) ? \
818 (!(sInB((ChP)->CtlP->AiopIO[3]) & sBitMapSetTbl[(ChP)->ChanNum])) : \
833 #define sGetControllerIntStatus(CTLP) (sInB((CTLP)->MReg1IO) & 0x0f)
847 ((CTLP)->isUPCI ? \
848 (sInW((CTLP)->PCIIO2) & UPCI_AIOP_INTR_BITS) : \
849 ((sInW((CTLP)->PCIIO) >> 8) & AIOP_INTR_BITS))
861 #define sGetRxCnt(ChP) sInW((ChP)->TxRxCount)
872 #define sGetTxCnt(ChP) sInB((ByteIO_t)(ChP)->TxRxCount)
881 #define sGetTxRxDataIO(ChP) (ChP)->TxRxData
894 (ChP)->CtlP = NULLCTLPTR; \
895 (ChP)->AiopNum = NULLAIOP; \
896 (ChP)->ChanID = AIOPID_NULL; \
897 (ChP)->ChanNum = NULLCHAN; \
909 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,RESET_ALL); \
910 sOutB((CTLP)->AiopIO[(AIOPNUM)]+_CMD_REG,0x0); \
921 (ChP)->TxControl[3] |= SETBREAK; \
922 out32((ChP)->IndexAddr,(ChP)->TxControl); \
934 (ChP)->BaudDiv[2] = (Byte_t)(DIVISOR); \
935 (ChP)->BaudDiv[3] = (Byte_t)((DIVISOR) >> 8); \
936 out32((ChP)->IndexAddr,(ChP)->BaudDiv); \
947 (ChP)->TxControl[2] &= ~DATA8BIT; \
948 out32((ChP)->IndexAddr,(ChP)->TxControl); \
959 (ChP)->TxControl[2] |= DATA8BIT; \
960 out32((ChP)->IndexAddr,(ChP)->TxControl); \
971 (ChP)->TxControl[3] |= SET_DTR; \
972 out32((ChP)->IndexAddr,(ChP)->TxControl); \
988 (ChP)->TxControl[2] |= EVEN_PAR; \
989 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1005 (ChP)->TxControl[2] &= ~EVEN_PAR; \
1006 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1011 Purpose: Set the RTS output
1017 if ((ChP)->rtsToggle) break; \
1018 (ChP)->TxControl[3] |= SET_RTS; \
1019 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1043 (ChP)->RxControl[2] &= ~TRIG_MASK; \
1044 (ChP)->RxControl[2] |= LEVEL; \
1045 out32((ChP)->IndexAddr,(ChP)->RxControl); \
1056 (ChP)->TxControl[2] &= ~STOP2; \
1057 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1068 (ChP)->TxControl[2] |= STOP2; \
1069 out32((ChP)->IndexAddr,(ChP)->TxControl); \
1081 (ChP)->R[0x07] = (CH); \
1082 out32((ChP)->IndexAddr,&(ChP)->R[0x04]); \
1094 (ChP)->R[0x0b] = (CH); \
1095 out32((ChP)->IndexAddr,&(ChP)->R[0x08]); \
1108 #define sStartRxProcessor(ChP) out32((ChP)->IndexAddr,&(ChP)->R[0])
1124 * This code is Copyright Theodore Ts'o, 1995-1997