Lines Matching refs:sOutW
1870 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */ in sPCIInitController()
2610 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */ in sInitController()
2667 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */ in sReadAiopNumChan()
2669 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */ in sReadAiopNumChan()
2798 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */ in sInitChan()
2799 sOutW(ChP->IndexData, 0); in sInitChan()
2805 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */ in sInitChan()
2806 sOutW(ChP->IndexData, 0); in sInitChan()
2807 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */ in sInitChan()
2808 sOutW(ChP->IndexData, 0); in sInitChan()
2810 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt); in sInitChan()
2813 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr); in sInitChan()
2884 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */ in sFlushRxFIFO()
2885 sOutW(ChP->IndexData, 0); in sFlushRxFIFO()
2886 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */ in sFlushRxFIFO()
2887 sOutW(ChP->IndexData, 0); in sFlushRxFIFO()
2926 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */ in sFlushTxFIFO()
2927 sOutW(ChP->IndexData, 0); in sFlushTxFIFO()
2954 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */ in sWriteTxPrioByte()