Lines Matching +full:0 +full:x740
29 TB_SWITCH_CAP_TMU = 0x03,
30 TB_SWITCH_CAP_VSE = 0x05,
34 TB_VSE_CAP_PLUG_EVENTS = 0x01, /* also EEPROM */
35 TB_VSE_CAP_TIME2 = 0x03,
36 TB_VSE_CAP_IECS = 0x04,
37 TB_VSE_CAP_LINK_CONTROLLER = 0x06, /* also IECS */
41 TB_PORT_CAP_PHY = 0x01,
42 TB_PORT_CAP_POWER = 0x02,
43 TB_PORT_CAP_TIME1 = 0x03,
44 TB_PORT_CAP_ADAP = 0x04,
45 TB_PORT_CAP_VSE = 0x05,
46 TB_PORT_CAP_USB4 = 0x06,
50 TB_PORT_DISABLED = 0, /* tb_cap_phy.disable == 1 */
61 u8 cap; /* if cap == 0x05 then we have a extended capability */
137 bool access_low:1; /* set to 0 before access */
141 bool not_present:1; /* should be 0 */
161 /* Present on port 0 in TB_CFG_SWITCH at address zero. */
163 /* DWORD 0 */
181 * milliseconds. Writing 0x00 is interpreted
190 #define USB4_VERSION_1_0 0x20
192 #define ROUTER_CS_1 0x01
193 #define ROUTER_CS_4 0x04
194 #define ROUTER_CS_5 0x05
195 #define ROUTER_CS_5_SLP BIT(0)
203 #define ROUTER_CS_6 0x06
204 #define ROUTER_CS_6_SLPR BIT(0)
210 #define ROUTER_CS_7 0x07
211 #define ROUTER_CS_9 0x09
212 #define ROUTER_CS_25 0x19
213 #define ROUTER_CS_26 0x1a
220 #define TMU_RTR_CS_0 0x00
223 #define TMU_RTR_CS_1 0x01
226 #define TMU_RTR_CS_2 0x02
227 #define TMU_RTR_CS_3 0x03
228 #define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK GENMASK(15, 0)
231 #define TMU_RTR_CS_22 0x16
232 #define TMU_RTR_CS_24 0x18
235 TB_TYPE_INACTIVE = 0x000000,
236 TB_TYPE_PORT = 0x000001,
237 TB_TYPE_NHI = 0x000002,
238 /* TB_TYPE_ETHERNET = 0x020000, lower order bits are not known */
239 /* TB_TYPE_SATA = 0x080000, lower order bits are not known */
240 TB_TYPE_DP_HDMI_IN = 0x0e0101,
241 TB_TYPE_DP_HDMI_OUT = 0x0e0102,
242 TB_TYPE_PCIE_DOWN = 0x100101,
243 TB_TYPE_PCIE_UP = 0x100102,
244 TB_TYPE_USB3_DOWN = 0x200101,
245 TB_TYPE_USB3_UP = 0x200102,
250 /* DWORD 0 */
280 #define ADP_CS_4 0x04
281 #define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0)
285 #define ADP_CS_5 0x05
290 #define TMU_ADP_CS_3 0x03
294 #define LANE_ADP_CS_0 0x00
297 #define LANE_ADP_CS_1 0x01
300 #define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1
301 #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3
306 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN2 0x8
307 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN3 0x4
312 #define PORT_CS_1 0x01
321 #define PORT_CS_2 0x02
322 #define PORT_CS_18 0x12
326 #define PORT_CS_19 0x13
334 #define ADP_DP_CS_0 0x00
339 #define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0)
342 #define ADP_DP_CS_2 0x02
344 #define ADP_DP_CS_3 0x03
346 #define DP_LOCAL_CAP 0x04
347 #define DP_REMOTE_CAP 0x05
348 #define DP_STATUS_CTRL 0x06
351 #define DP_COMMON_CAP 0x07
358 #define DP_COMMON_CAP_RATE_RBR 0x0
359 #define DP_COMMON_CAP_RATE_HBR 0x1
360 #define DP_COMMON_CAP_RATE_HBR2 0x2
361 #define DP_COMMON_CAP_RATE_HBR3 0x3
364 #define DP_COMMON_CAP_1_LANE 0x0
365 #define DP_COMMON_CAP_2_LANES 0x1
366 #define DP_COMMON_CAP_4_LANES 0x2
370 #define ADP_PCIE_CS_0 0x00
374 #define ADP_USB3_CS_0 0x00
377 #define ADP_USB3_CS_1 0x01
378 #define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0)
382 #define ADP_USB3_CS_2 0x02
383 #define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0)
387 #define ADP_USB3_CS_3 0x03
388 #define ADP_USB3_CS_3_SCALE_MASK GENMASK(5, 0)
389 #define ADP_USB3_CS_4 0x04
390 #define ADP_USB3_CS_4_ALR_MASK GENMASK(6, 0)
391 #define ADP_USB3_CS_4_ALR_20G 0x1
395 #define ADP_USB3_CS_4_MSLR_20G 0x1
399 /* DWORD 0 */
425 #define TB_LC_DESC 0x02
426 #define TB_LC_DESC_NLC_MASK GENMASK(3, 0)
431 #define TB_LC_FUSE 0x03
432 #define TB_LC_SNK_ALLOCATION 0x10
433 #define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0)
434 #define TB_LC_SNK_ALLOCATION_SNK0_CM 0x1
437 #define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1
438 #define TB_LC_POWER 0x740
441 #define TB_LC_PORT_ATTR 0x8d
444 #define TB_LC_SX_CTRL 0x96